forked from Minki/linux
e986211827
Add MT2701 clock support, include topckgen, apmixedsys, infracfg, pericfg and subsystem clocks. Signed-off-by: Shunli Wang <shunli.wang@mediatek.com> Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Tested-by: John Crispin <blogic@openwrt.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
53 lines
1.3 KiB
C
53 lines
1.3 KiB
C
/*
|
|
* Copyright (c) 2014 MediaTek Inc.
|
|
* Author: James Liao <jamesjj.liao@mediatek.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
|
|
#ifndef __DRV_CLK_GATE_H
|
|
#define __DRV_CLK_GATE_H
|
|
|
|
#include <linux/regmap.h>
|
|
#include <linux/clk-provider.h>
|
|
|
|
struct clk;
|
|
|
|
struct mtk_clk_gate {
|
|
struct clk_hw hw;
|
|
struct regmap *regmap;
|
|
int set_ofs;
|
|
int clr_ofs;
|
|
int sta_ofs;
|
|
u8 bit;
|
|
};
|
|
|
|
static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw)
|
|
{
|
|
return container_of(hw, struct mtk_clk_gate, hw);
|
|
}
|
|
|
|
extern const struct clk_ops mtk_clk_gate_ops_setclr;
|
|
extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
|
|
extern const struct clk_ops mtk_clk_gate_ops_no_setclr;
|
|
extern const struct clk_ops mtk_clk_gate_ops_no_setclr_inv;
|
|
|
|
struct clk *mtk_clk_register_gate(
|
|
const char *name,
|
|
const char *parent_name,
|
|
struct regmap *regmap,
|
|
int set_ofs,
|
|
int clr_ofs,
|
|
int sta_ofs,
|
|
u8 bit,
|
|
const struct clk_ops *ops);
|
|
|
|
#endif /* __DRV_CLK_GATE_H */
|