eb4e52b3f3
We used to fill in rx skbs' frequency field by mac80211's current channel value. In some cases, mac80211 switches channel before all rx packets have been processed. This results in incorrect bss info. We fix this by filling in frequency field with channel index obtained from hardware, then fix potential cck missing issue by skb's original hw rate. After all fix is done, convert hw rate back to the supported band rate index. Signed-off-by: Po Hao Huang <phhuang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20211111023706.14154-3-pkshih@realtek.com
372 lines
11 KiB
C
372 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright(c) 2019-2020 Realtek Corporation
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*/
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#ifndef __RTW89_PHY_H__
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#define __RTW89_PHY_H__
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#include "core.h"
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#define RTW89_PHY_ADDR_OFFSET 0x10000
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#define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr)
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#define PHY_HEADLINE_VALID 0xf
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#define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr)
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#define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \
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FIELD_PREP(GENMASK(7, 0), cv))
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#define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr)
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#define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr)
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#define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr)
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#define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr)
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#define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; })
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#define PHY_COND_BRANCH_IF 0x8
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#define PHY_COND_BRANCH_ELIF 0x9
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#define PHY_COND_BRANCH_ELSE 0xa
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#define PHY_COND_BRANCH_END 0xb
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#define PHY_COND_CHECK 0x4
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#define PHY_COND_DONT_CARE 0xff
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#define RA_MASK_CCK_RATES GENMASK_ULL(3, 0)
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#define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4)
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#define RA_MASK_SUBCCK_RATES 0x5ULL
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#define RA_MASK_SUBOFDM_RATES 0x10ULL
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#define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12)
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#define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24)
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#define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36)
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#define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48)
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#define RA_MASK_HT_RATES GENMASK_ULL(55, 12)
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#define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12)
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#define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24)
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#define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36)
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#define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48)
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#define RA_MASK_VHT_RATES GENMASK_ULL(57, 12)
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#define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12)
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#define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24)
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#define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36)
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#define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48)
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#define RA_MASK_HE_RATES GENMASK_ULL(59, 12)
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#define CFO_TRK_ENABLE_TH (2 << 2)
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#define CFO_TRK_STOP_TH_4 (30 << 2)
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#define CFO_TRK_STOP_TH_3 (20 << 2)
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#define CFO_TRK_STOP_TH_2 (10 << 2)
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#define CFO_TRK_STOP_TH_1 (00 << 2)
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#define CFO_TRK_STOP_TH (2 << 2)
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#define CFO_SW_COMP_FINE_TUNE (2 << 2)
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#define CFO_PERIOD_CNT 15
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#define CFO_TP_UPPER 100
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#define CFO_TP_LOWER 50
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#define CFO_COMP_PERIOD 250
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#define CFO_COMP_WEIGHT 8
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#define MAX_CFO_TOLERANCE 30
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#define CCX_MAX_PERIOD 2097
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#define CCX_MAX_PERIOD_UNIT 32
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#define MS_TO_4US_RATIO 250
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#define ENV_MNTR_FAIL_DWORD 0xffffffff
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#define ENV_MNTR_IFSCLM_HIS_MAX 127
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#define PERMIL 1000
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#define PERCENT 100
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#define IFS_CLM_TH0_UPPER 64
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#define IFS_CLM_TH_MUL 4
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#define IFS_CLM_TH_START_IDX 0
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#define TIA0_GAIN_A 12
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#define TIA0_GAIN_G 16
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#define LNA0_GAIN (-24)
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#define U4_MAX_BIT 3
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#define U8_MAX_BIT 7
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#define DIG_GAIN_SHIFT 2
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#define DIG_GAIN 8
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#define LNA_IDX_MAX 6
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#define LNA_IDX_MIN 0
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#define TIA_IDX_MAX 1
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#define TIA_IDX_MIN 0
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#define RXB_IDX_MAX 31
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#define RXB_IDX_MIN 0
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#define PD_TH_MAX_RSSI 70
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#define PD_TH_MIN_RSSI 8
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#define PD_TH_BW80_CMP_VAL 6
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#define PD_TH_BW40_CMP_VAL 3
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#define PD_TH_BW20_CMP_VAL 0
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#define PD_TH_CMP_VAL 3
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#define PD_TH_SB_FLTR_CMP_VAL 7
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#define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT)
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#define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL)
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#define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA)
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#define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD)
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#define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA)
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enum rtw89_phy_c2h_ra_func {
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RTW89_PHY_C2H_FUNC_STS_RPT,
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RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT,
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RTW89_PHY_C2H_FUNC_TXSTS,
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RTW89_PHY_C2H_FUNC_RA_MAX,
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};
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enum rtw89_phy_c2h_class {
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RTW89_PHY_C2H_CLASS_RUA,
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RTW89_PHY_C2H_CLASS_RA,
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RTW89_PHY_C2H_CLASS_DM,
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RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10,
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RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17,
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RTW89_PHY_C2H_CLASS_MAX,
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};
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enum rtw89_env_monitor_result_level {
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RTW89_PHY_ENV_MON_CCX_FAIL = 0,
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RTW89_PHY_ENV_MON_NHM = BIT(0),
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RTW89_PHY_ENV_MON_CLM = BIT(1),
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RTW89_PHY_ENV_MON_FAHM = BIT(2),
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RTW89_PHY_ENV_MON_IFS_CLM = BIT(3),
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RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4),
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};
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#define CCX_US_BASE_RATIO 4
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enum rtw89_ccx_unit {
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RTW89_CCX_4_US = 0,
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RTW89_CCX_8_US = 1,
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RTW89_CCX_16_US = 2,
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RTW89_CCX_32_US = 3
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};
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enum rtw89_phy_status_ie_type {
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RTW89_PHYSTS_IE00_CMN_CCK = 0,
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RTW89_PHYSTS_IE01_CMN_OFDM = 1,
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RTW89_PHYSTS_IE02_CMN_EXT_AX = 2,
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RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3,
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RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4,
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RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5,
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RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6,
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RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7,
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RTW89_PHYSTS_IE08_FTR_CH = 8,
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RTW89_PHYSTS_IE09_FTR_0 = 9,
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RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10,
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RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11,
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RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12,
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RTW89_PHYSTS_IE13_DL_MU_DEF = 13,
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RTW89_PHYSTS_IE14_TB_UL_CQI = 14,
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RTW89_PHYSTS_IE15_TB_UL_DEF = 15,
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RTW89_PHYSTS_IE16_RSVD16 = 16,
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RTW89_PHYSTS_IE17_TB_UL_CTRL = 17,
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RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18,
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RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19,
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RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20,
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RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21,
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RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22,
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RTW89_PHYSTS_IE23_RSVD23 = 23,
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RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24,
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RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25,
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RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26,
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RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27,
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RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28,
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RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29,
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RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30,
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RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31,
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/* keep last */
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RTW89_PHYSTS_IE_NUM,
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RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1
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};
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enum rtw89_phy_status_bitmap {
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RTW89_TD_SEARCH_FAIL = 0,
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RTW89_BRK_BY_TX_PKT = 1,
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RTW89_CCA_SPOOF = 2,
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RTW89_OFDM_BRK = 3,
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RTW89_CCK_BRK = 4,
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RTW89_DL_MU_SPOOFING = 5,
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RTW89_HE_MU = 6,
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RTW89_VHT_MU = 7,
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RTW89_UL_TB_SPOOFING = 8,
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RTW89_RSVD_9 = 9,
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RTW89_TRIG_BASE_PPDU = 10,
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RTW89_CCK_PKT = 11,
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RTW89_LEGACY_OFDM_PKT = 12,
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RTW89_HT_PKT = 13,
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RTW89_VHT_PKT = 14,
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RTW89_HE_PKT = 15,
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RTW89_PHYSTS_BITMAP_NUM
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};
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enum rtw89_dig_gain_type {
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RTW89_DIG_GAIN_LNA_G = 0,
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RTW89_DIG_GAIN_TIA_G = 1,
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RTW89_DIG_GAIN_LNA_A = 2,
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RTW89_DIG_GAIN_TIA_A = 3,
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RTW89_DIG_GAIN_MAX = 4
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};
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enum rtw89_dig_gain_lna_idx {
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RTW89_DIG_GAIN_LNA_IDX1 = 1,
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RTW89_DIG_GAIN_LNA_IDX2 = 2,
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RTW89_DIG_GAIN_LNA_IDX3 = 3,
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RTW89_DIG_GAIN_LNA_IDX4 = 4,
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RTW89_DIG_GAIN_LNA_IDX5 = 5,
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RTW89_DIG_GAIN_LNA_IDX6 = 6
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};
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enum rtw89_dig_gain_tia_idx {
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RTW89_DIG_GAIN_TIA_IDX0 = 0,
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RTW89_DIG_GAIN_TIA_IDX1 = 1
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};
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struct rtw89_txpwr_byrate_cfg {
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enum rtw89_band band;
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enum rtw89_nss nss;
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enum rtw89_rate_section rs;
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u8 shf;
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u8 len;
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u32 data;
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};
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#define DELTA_SWINGIDX_SIZE 30
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struct rtw89_txpwr_track_cfg {
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const u8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE];
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const u8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE];
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const u8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE];
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const u8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE];
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const u8 *delta_swingidx_2gb_n;
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const u8 *delta_swingidx_2gb_p;
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const u8 *delta_swingidx_2ga_n;
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const u8 *delta_swingidx_2ga_p;
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const u8 *delta_swingidx_2g_cck_b_n;
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const u8 *delta_swingidx_2g_cck_b_p;
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const u8 *delta_swingidx_2g_cck_a_n;
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const u8 *delta_swingidx_2g_cck_a_p;
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};
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struct rtw89_phy_dig_gain_cfg {
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const struct rtw89_reg_def *table;
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u8 size;
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};
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struct rtw89_phy_dig_gain_table {
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const struct rtw89_phy_dig_gain_cfg *cfg_lna_g;
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const struct rtw89_phy_dig_gain_cfg *cfg_tia_g;
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const struct rtw89_phy_dig_gain_cfg *cfg_lna_a;
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const struct rtw89_phy_dig_gain_cfg *cfg_tia_a;
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};
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struct rtw89_phy_reg3_tbl {
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const struct rtw89_reg3_def *reg3;
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int size;
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};
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#define DECLARE_PHY_REG3_TBL(_name) \
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const struct rtw89_phy_reg3_tbl _name ## _tbl = { \
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.reg3 = _name, \
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.size = ARRAY_SIZE(_name), \
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}
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static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev,
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u32 addr, u8 data)
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{
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rtw89_write8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data);
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}
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static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev,
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u32 addr, u16 data)
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{
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rtw89_write16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data);
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}
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static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev,
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u32 addr, u32 data)
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{
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rtw89_write32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data);
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}
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static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev,
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u32 addr, u32 bits)
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{
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rtw89_write32_set(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits);
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}
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static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev,
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u32 addr, u32 bits)
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{
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rtw89_write32_clr(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits);
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}
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static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev,
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u32 addr, u32 mask, u32 data)
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{
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rtw89_write32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask, data);
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}
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static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr)
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{
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return rtw89_read8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET);
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}
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static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr)
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{
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return rtw89_read16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET);
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}
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static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr)
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{
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return rtw89_read32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET);
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}
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static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev,
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u32 addr, u32 mask)
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{
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return rtw89_read32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask);
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}
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void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
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const struct rtw89_phy_reg3_tbl *tbl);
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u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
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struct rtw89_channel_params *param,
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enum rtw89_bandwidth dbw);
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u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
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u32 addr, u32 mask);
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bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
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u32 addr, u32 mask, u32 data);
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void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev);
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void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev);
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void rtw89_phy_dm_init(struct rtw89_dev *rtwdev);
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void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
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u32 data, enum rtw89_phy_idx phy_idx);
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void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
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const struct rtw89_txpwr_table *tbl);
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s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev,
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const struct rtw89_rate_desc *rate_desc);
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void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev,
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struct rtw89_txpwr_limit *lmt,
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u8 ntx);
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void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev,
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struct rtw89_txpwr_limit_ru *lmt_ru,
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u8 ntx);
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s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev,
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u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch);
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void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta);
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void rtw89_phy_ra_update(struct rtw89_dev *rtwdev);
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void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta);
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void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
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struct ieee80211_vif *vif,
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const struct cfg80211_bitrate_mask *mask);
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void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
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u32 len, u8 class, u8 func);
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void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev);
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void rtw89_phy_cfo_track_work(struct work_struct *work);
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void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
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struct rtw89_rx_phy_ppdu *phy_ppdu);
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void rtw89_phy_stat_track(struct rtw89_dev *rtwdev);
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void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev);
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void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
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u32 val);
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void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev);
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void rtw89_phy_dig(struct rtw89_dev *rtwdev);
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void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
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#endif
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