8f187163eb
Some NVIDIA GPUs do not support direct atomic access to system memory via PCIe. Instead this must be emulated by granting the GPU exclusive access to the memory. This is achieved by replacing CPU page table entries with special swap entries that fault on userspace access. The driver then grants the GPU permission to update the page undergoing atomic access via the GPU page tables. When CPU access to the page is required a CPU fault is raised which calls into the device driver via MMU notifiers to revoke the atomic access. The original page table entries are then restored allowing CPU access to proceed. Link: https://lkml.kernel.org/r/20210616105937.23201-11-apopple@nvidia.com Signed-off-by: Alistair Popple <apopple@nvidia.com> Reviewed-by: Ben Skeggs <bskeggs@redhat.com> Cc: Christoph Hellwig <hch@lst.de> Cc: Hugh Dickins <hughd@google.com> Cc: Jason Gunthorpe <jgg@nvidia.com> Cc: John Hubbard <jhubbard@nvidia.com> Cc: "Matthew Wilcox (Oracle)" <willy@infradead.org> Cc: Peter Xu <peterx@redhat.com> Cc: Ralph Campbell <rcampbell@nvidia.com> Cc: Shakeel Butt <shakeelb@google.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
94 lines
2.5 KiB
C
94 lines
2.5 KiB
C
#ifndef __NVIF_IF000C_H__
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#define __NVIF_IF000C_H__
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struct nvif_vmm_v0 {
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__u8 version;
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__u8 page_nr;
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__u8 managed;
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__u8 pad03[5];
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__u64 addr;
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__u64 size;
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__u8 data[];
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};
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#define NVIF_VMM_V0_PAGE 0x00
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#define NVIF_VMM_V0_GET 0x01
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#define NVIF_VMM_V0_PUT 0x02
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#define NVIF_VMM_V0_MAP 0x03
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#define NVIF_VMM_V0_UNMAP 0x04
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#define NVIF_VMM_V0_PFNMAP 0x05
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#define NVIF_VMM_V0_PFNCLR 0x06
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#define NVIF_VMM_V0_MTHD(i) ((i) + 0x80)
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struct nvif_vmm_page_v0 {
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__u8 version;
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__u8 index;
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__u8 shift;
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__u8 sparse;
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__u8 vram;
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__u8 host;
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__u8 comp;
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__u8 pad07[1];
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};
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struct nvif_vmm_get_v0 {
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__u8 version;
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#define NVIF_VMM_GET_V0_ADDR 0x00
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#define NVIF_VMM_GET_V0_PTES 0x01
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#define NVIF_VMM_GET_V0_LAZY 0x02
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__u8 type;
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__u8 sparse;
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__u8 page;
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__u8 align;
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__u8 pad05[3];
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__u64 size;
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__u64 addr;
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};
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struct nvif_vmm_put_v0 {
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__u8 version;
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__u8 pad01[7];
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__u64 addr;
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};
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struct nvif_vmm_map_v0 {
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__u8 version;
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__u8 pad01[7];
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__u64 addr;
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__u64 size;
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__u64 memory;
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__u64 offset;
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__u8 data[];
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};
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struct nvif_vmm_unmap_v0 {
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__u8 version;
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__u8 pad01[7];
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__u64 addr;
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};
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struct nvif_vmm_pfnmap_v0 {
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__u8 version;
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__u8 page;
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__u8 pad02[6];
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__u64 addr;
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__u64 size;
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#define NVIF_VMM_PFNMAP_V0_ADDR 0xfffffffffffff000ULL
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#define NVIF_VMM_PFNMAP_V0_ADDR_SHIFT 12
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#define NVIF_VMM_PFNMAP_V0_APER 0x00000000000000f0ULL
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#define NVIF_VMM_PFNMAP_V0_HOST 0x0000000000000000ULL
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#define NVIF_VMM_PFNMAP_V0_VRAM 0x0000000000000010ULL
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#define NVIF_VMM_PFNMAP_V0_A 0x0000000000000004ULL
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#define NVIF_VMM_PFNMAP_V0_W 0x0000000000000002ULL
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#define NVIF_VMM_PFNMAP_V0_V 0x0000000000000001ULL
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#define NVIF_VMM_PFNMAP_V0_NONE 0x0000000000000000ULL
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__u64 phys[];
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};
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struct nvif_vmm_pfnclr_v0 {
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__u8 version;
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__u8 pad01[7];
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__u64 addr;
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__u64 size;
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};
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#endif
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