f4510a2752
Now that CRTC's have a primary plane, there's no need to track the
framebuffer in the CRTC. Replace all references to the CRTC fb with the
primary plane's fb.
This patch was generated by the Coccinelle semantic patching tool using
the following rules:
@@ struct drm_crtc C; @@
- (C).fb
+ C.primary->fb
@@ struct drm_crtc *C; @@
- (C)->fb
+ C->primary->fb
v3: Generate patch via coccinelle. Actual removal of crtc->fb has been
moved to a subsequent patch.
v2: Fixup several lingering crtc->fb instances that were missed in the
first patch iteration. [Rob Clark]
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
810 lines
22 KiB
C
810 lines
22 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "mdp4_kms.h"
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#include <drm/drm_mode.h>
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#include "drm_crtc.h"
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#include "drm_crtc_helper.h"
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#include "drm_flip_work.h"
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struct mdp4_crtc {
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struct drm_crtc base;
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char name[8];
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struct drm_plane *plane;
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struct drm_plane *planes[8];
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int id;
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int ovlp;
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enum mdp4_dma dma;
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bool enabled;
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/* which mixer/encoder we route output to: */
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int mixer;
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struct {
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spinlock_t lock;
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bool stale;
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uint32_t width, height;
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uint32_t x, y;
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/* next cursor to scan-out: */
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uint32_t next_iova;
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struct drm_gem_object *next_bo;
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/* current cursor being scanned out: */
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struct drm_gem_object *scanout_bo;
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} cursor;
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/* if there is a pending flip, these will be non-null: */
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struct drm_pending_vblank_event *event;
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struct msm_fence_cb pageflip_cb;
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#define PENDING_CURSOR 0x1
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#define PENDING_FLIP 0x2
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atomic_t pending;
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/* the fb that we logically (from PoV of KMS API) hold a ref
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* to. Which we may not yet be scanning out (we may still
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* be scanning out previous in case of page_flip while waiting
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* for gpu rendering to complete:
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*/
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struct drm_framebuffer *fb;
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/* the fb that we currently hold a scanout ref to: */
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struct drm_framebuffer *scanout_fb;
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/* for unref'ing framebuffers after scanout completes: */
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struct drm_flip_work unref_fb_work;
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/* for unref'ing cursor bo's after scanout completes: */
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struct drm_flip_work unref_cursor_work;
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struct mdp_irq vblank;
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struct mdp_irq err;
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};
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#define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base)
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static struct mdp4_kms *get_kms(struct drm_crtc *crtc)
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{
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struct msm_drm_private *priv = crtc->dev->dev_private;
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return to_mdp4_kms(to_mdp_kms(priv->kms));
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}
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static void request_pending(struct drm_crtc *crtc, uint32_t pending)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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atomic_or(pending, &mdp4_crtc->pending);
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mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
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}
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static void crtc_flush(struct drm_crtc *crtc)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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struct mdp4_kms *mdp4_kms = get_kms(crtc);
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uint32_t i, flush = 0;
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for (i = 0; i < ARRAY_SIZE(mdp4_crtc->planes); i++) {
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struct drm_plane *plane = mdp4_crtc->planes[i];
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if (plane) {
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enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
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flush |= pipe2flush(pipe_id);
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}
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}
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flush |= ovlp2flush(mdp4_crtc->ovlp);
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DBG("%s: flush=%08x", mdp4_crtc->name, flush);
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mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);
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}
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static void update_fb(struct drm_crtc *crtc, struct drm_framebuffer *new_fb)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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struct drm_framebuffer *old_fb = mdp4_crtc->fb;
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/* grab reference to incoming scanout fb: */
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drm_framebuffer_reference(new_fb);
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mdp4_crtc->base.primary->fb = new_fb;
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mdp4_crtc->fb = new_fb;
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if (old_fb)
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drm_flip_work_queue(&mdp4_crtc->unref_fb_work, old_fb);
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}
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/* unlike update_fb(), take a ref to the new scanout fb *before* updating
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* plane, then call this. Needed to ensure we don't unref the buffer that
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* is actually still being scanned out.
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*
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* Note that this whole thing goes away with atomic.. since we can defer
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* calling into driver until rendering is done.
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*/
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static void update_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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/* flush updates, to make sure hw is updated to new scanout fb,
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* so that we can safely queue unref to current fb (ie. next
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* vblank we know hw is done w/ previous scanout_fb).
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*/
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crtc_flush(crtc);
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if (mdp4_crtc->scanout_fb)
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drm_flip_work_queue(&mdp4_crtc->unref_fb_work,
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mdp4_crtc->scanout_fb);
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mdp4_crtc->scanout_fb = fb;
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/* enable vblank to complete flip: */
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request_pending(crtc, PENDING_FLIP);
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}
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/* if file!=NULL, this is preclose potential cancel-flip path */
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static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_pending_vblank_event *event;
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unsigned long flags;
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spin_lock_irqsave(&dev->event_lock, flags);
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event = mdp4_crtc->event;
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if (event) {
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/* if regular vblank case (!file) or if cancel-flip from
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* preclose on file that requested flip, then send the
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* event:
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*/
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if (!file || (event->base.file_priv == file)) {
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mdp4_crtc->event = NULL;
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drm_send_vblank_event(dev, mdp4_crtc->id, event);
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}
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}
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spin_unlock_irqrestore(&dev->event_lock, flags);
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}
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static void pageflip_cb(struct msm_fence_cb *cb)
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{
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struct mdp4_crtc *mdp4_crtc =
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container_of(cb, struct mdp4_crtc, pageflip_cb);
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struct drm_crtc *crtc = &mdp4_crtc->base;
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struct drm_framebuffer *fb = crtc->primary->fb;
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if (!fb)
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return;
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drm_framebuffer_reference(fb);
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mdp4_plane_set_scanout(mdp4_crtc->plane, fb);
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update_scanout(crtc, fb);
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}
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static void unref_fb_worker(struct drm_flip_work *work, void *val)
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{
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struct mdp4_crtc *mdp4_crtc =
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container_of(work, struct mdp4_crtc, unref_fb_work);
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struct drm_device *dev = mdp4_crtc->base.dev;
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mutex_lock(&dev->mode_config.mutex);
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drm_framebuffer_unreference(val);
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mutex_unlock(&dev->mode_config.mutex);
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}
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static void unref_cursor_worker(struct drm_flip_work *work, void *val)
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{
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struct mdp4_crtc *mdp4_crtc =
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container_of(work, struct mdp4_crtc, unref_cursor_work);
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struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);
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msm_gem_put_iova(val, mdp4_kms->id);
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drm_gem_object_unreference_unlocked(val);
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}
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static void mdp4_crtc_destroy(struct drm_crtc *crtc)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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mdp4_crtc->plane->funcs->destroy(mdp4_crtc->plane);
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drm_crtc_cleanup(crtc);
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drm_flip_work_cleanup(&mdp4_crtc->unref_fb_work);
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drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work);
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kfree(mdp4_crtc);
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}
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static void mdp4_crtc_dpms(struct drm_crtc *crtc, int mode)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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struct mdp4_kms *mdp4_kms = get_kms(crtc);
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bool enabled = (mode == DRM_MODE_DPMS_ON);
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DBG("%s: mode=%d", mdp4_crtc->name, mode);
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if (enabled != mdp4_crtc->enabled) {
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if (enabled) {
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mdp4_enable(mdp4_kms);
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mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err);
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} else {
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mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err);
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mdp4_disable(mdp4_kms);
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}
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mdp4_crtc->enabled = enabled;
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}
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}
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static bool mdp4_crtc_mode_fixup(struct drm_crtc *crtc,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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return true;
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}
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static void blend_setup(struct drm_crtc *crtc)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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struct mdp4_kms *mdp4_kms = get_kms(crtc);
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int i, ovlp = mdp4_crtc->ovlp;
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uint32_t mixer_cfg = 0;
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static const enum mdp_mixer_stage_id stages[] = {
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STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
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};
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/* statically (for now) map planes to mixer stage (z-order): */
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static const int idxs[] = {
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[VG1] = 1,
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[VG2] = 2,
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[RGB1] = 0,
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[RGB2] = 0,
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[RGB3] = 0,
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[VG3] = 3,
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[VG4] = 4,
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};
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bool alpha[4]= { false, false, false, false };
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);
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/* TODO single register for all CRTCs, so this won't work properly
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* when multiple CRTCs are active..
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*/
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for (i = 0; i < ARRAY_SIZE(mdp4_crtc->planes); i++) {
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struct drm_plane *plane = mdp4_crtc->planes[i];
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if (plane) {
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enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
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int idx = idxs[pipe_id];
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if (idx > 0) {
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const struct mdp_format *format =
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to_mdp_format(msm_framebuffer_format(plane->fb));
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alpha[idx-1] = format->alpha_enable;
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}
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mixer_cfg |= mixercfg(mdp4_crtc->mixer, pipe_id, stages[idx]);
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}
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}
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/* this shouldn't happen.. and seems to cause underflow: */
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WARN_ON(!mixer_cfg);
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for (i = 0; i < 4; i++) {
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uint32_t op;
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if (alpha[i]) {
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op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) |
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MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) |
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MDP4_OVLP_STAGE_OP_BG_INV_ALPHA;
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} else {
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op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) |
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MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST);
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}
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);
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}
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mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);
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}
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static int mdp4_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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int x, int y,
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struct drm_framebuffer *old_fb)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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struct mdp4_kms *mdp4_kms = get_kms(crtc);
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enum mdp4_dma dma = mdp4_crtc->dma;
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int ret, ovlp = mdp4_crtc->ovlp;
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mode = adjusted_mode;
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DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
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mdp4_crtc->name, mode->base.id, mode->name,
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mode->vrefresh, mode->clock,
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mode->hdisplay, mode->hsync_start,
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mode->hsync_end, mode->htotal,
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mode->vdisplay, mode->vsync_start,
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mode->vsync_end, mode->vtotal,
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mode->type, mode->flags);
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/* grab extra ref for update_scanout() */
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drm_framebuffer_reference(crtc->primary->fb);
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ret = mdp4_plane_mode_set(mdp4_crtc->plane, crtc, crtc->primary->fb,
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0, 0, mode->hdisplay, mode->vdisplay,
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x << 16, y << 16,
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mode->hdisplay << 16, mode->vdisplay << 16);
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if (ret) {
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drm_framebuffer_unreference(crtc->primary->fb);
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dev_err(crtc->dev->dev, "%s: failed to set mode on plane: %d\n",
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mdp4_crtc->name, ret);
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return ret;
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}
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mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma),
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MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) |
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MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay));
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/* take data from pipe: */
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mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0);
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mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma),
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crtc->primary->fb->pitches[0]);
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mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma),
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MDP4_DMA_DST_SIZE_WIDTH(0) |
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MDP4_DMA_DST_SIZE_HEIGHT(0));
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),
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MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) |
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MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay));
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp),
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crtc->primary->fb->pitches[0]);
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mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);
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if (dma == DMA_E) {
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mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000);
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mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000);
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mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000);
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}
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update_fb(crtc, crtc->primary->fb);
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update_scanout(crtc, crtc->primary->fb);
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return 0;
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}
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static void mdp4_crtc_prepare(struct drm_crtc *crtc)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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DBG("%s", mdp4_crtc->name);
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/* make sure we hold a ref to mdp clks while setting up mode: */
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mdp4_enable(get_kms(crtc));
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mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
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}
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static void mdp4_crtc_commit(struct drm_crtc *crtc)
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{
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mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
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crtc_flush(crtc);
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/* drop the ref to mdp clk's that we got in prepare: */
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mdp4_disable(get_kms(crtc));
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}
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static int mdp4_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
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struct drm_framebuffer *old_fb)
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{
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struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
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struct drm_plane *plane = mdp4_crtc->plane;
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struct drm_display_mode *mode = &crtc->mode;
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int ret;
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/* grab extra ref for update_scanout() */
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drm_framebuffer_reference(crtc->primary->fb);
|
|
|
|
ret = mdp4_plane_mode_set(plane, crtc, crtc->primary->fb,
|
|
0, 0, mode->hdisplay, mode->vdisplay,
|
|
x << 16, y << 16,
|
|
mode->hdisplay << 16, mode->vdisplay << 16);
|
|
if (ret) {
|
|
drm_framebuffer_unreference(crtc->primary->fb);
|
|
return ret;
|
|
}
|
|
|
|
update_fb(crtc, crtc->primary->fb);
|
|
update_scanout(crtc, crtc->primary->fb);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void mdp4_crtc_load_lut(struct drm_crtc *crtc)
|
|
{
|
|
}
|
|
|
|
static int mdp4_crtc_page_flip(struct drm_crtc *crtc,
|
|
struct drm_framebuffer *new_fb,
|
|
struct drm_pending_vblank_event *event,
|
|
uint32_t page_flip_flags)
|
|
{
|
|
struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
|
|
struct drm_device *dev = crtc->dev;
|
|
struct drm_gem_object *obj;
|
|
unsigned long flags;
|
|
|
|
if (mdp4_crtc->event) {
|
|
dev_err(dev->dev, "already pending flip!\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
obj = msm_framebuffer_bo(new_fb, 0);
|
|
|
|
spin_lock_irqsave(&dev->event_lock, flags);
|
|
mdp4_crtc->event = event;
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
|
|
update_fb(crtc, new_fb);
|
|
|
|
return msm_gem_queue_inactive_cb(obj, &mdp4_crtc->pageflip_cb);
|
|
}
|
|
|
|
static int mdp4_crtc_set_property(struct drm_crtc *crtc,
|
|
struct drm_property *property, uint64_t val)
|
|
{
|
|
// XXX
|
|
return -EINVAL;
|
|
}
|
|
|
|
#define CURSOR_WIDTH 64
|
|
#define CURSOR_HEIGHT 64
|
|
|
|
/* called from IRQ to update cursor related registers (if needed). The
|
|
* cursor registers, other than x/y position, appear not to be double
|
|
* buffered, and changing them other than from vblank seems to trigger
|
|
* underflow.
|
|
*/
|
|
static void update_cursor(struct drm_crtc *crtc)
|
|
{
|
|
struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
|
|
struct mdp4_kms *mdp4_kms = get_kms(crtc);
|
|
enum mdp4_dma dma = mdp4_crtc->dma;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
|
|
if (mdp4_crtc->cursor.stale) {
|
|
struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo;
|
|
struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo;
|
|
uint32_t iova = mdp4_crtc->cursor.next_iova;
|
|
|
|
if (next_bo) {
|
|
/* take a obj ref + iova ref when we start scanning out: */
|
|
drm_gem_object_reference(next_bo);
|
|
msm_gem_get_iova_locked(next_bo, mdp4_kms->id, &iova);
|
|
|
|
/* enable cursor: */
|
|
mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),
|
|
MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) |
|
|
MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height));
|
|
mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova);
|
|
mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
|
|
MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) |
|
|
MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN);
|
|
} else {
|
|
/* disable cursor: */
|
|
mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), 0);
|
|
mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
|
|
MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB));
|
|
}
|
|
|
|
/* and drop the iova ref + obj rev when done scanning out: */
|
|
if (prev_bo)
|
|
drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo);
|
|
|
|
mdp4_crtc->cursor.scanout_bo = next_bo;
|
|
mdp4_crtc->cursor.stale = false;
|
|
}
|
|
|
|
mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma),
|
|
MDP4_DMA_CURSOR_POS_X(mdp4_crtc->cursor.x) |
|
|
MDP4_DMA_CURSOR_POS_Y(mdp4_crtc->cursor.y));
|
|
|
|
spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
|
|
}
|
|
|
|
static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
|
|
struct drm_file *file_priv, uint32_t handle,
|
|
uint32_t width, uint32_t height)
|
|
{
|
|
struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
|
|
struct mdp4_kms *mdp4_kms = get_kms(crtc);
|
|
struct drm_device *dev = crtc->dev;
|
|
struct drm_gem_object *cursor_bo, *old_bo;
|
|
unsigned long flags;
|
|
uint32_t iova;
|
|
int ret;
|
|
|
|
if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
|
|
dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (handle) {
|
|
cursor_bo = drm_gem_object_lookup(dev, file_priv, handle);
|
|
if (!cursor_bo)
|
|
return -ENOENT;
|
|
} else {
|
|
cursor_bo = NULL;
|
|
}
|
|
|
|
if (cursor_bo) {
|
|
ret = msm_gem_get_iova(cursor_bo, mdp4_kms->id, &iova);
|
|
if (ret)
|
|
goto fail;
|
|
} else {
|
|
iova = 0;
|
|
}
|
|
|
|
spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
|
|
old_bo = mdp4_crtc->cursor.next_bo;
|
|
mdp4_crtc->cursor.next_bo = cursor_bo;
|
|
mdp4_crtc->cursor.next_iova = iova;
|
|
mdp4_crtc->cursor.width = width;
|
|
mdp4_crtc->cursor.height = height;
|
|
mdp4_crtc->cursor.stale = true;
|
|
spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
|
|
|
|
if (old_bo) {
|
|
/* drop our previous reference: */
|
|
msm_gem_put_iova(old_bo, mdp4_kms->id);
|
|
drm_gem_object_unreference_unlocked(old_bo);
|
|
}
|
|
|
|
crtc_flush(crtc);
|
|
request_pending(crtc, PENDING_CURSOR);
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
drm_gem_object_unreference_unlocked(cursor_bo);
|
|
return ret;
|
|
}
|
|
|
|
static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
|
|
{
|
|
struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
|
|
mdp4_crtc->cursor.x = x;
|
|
mdp4_crtc->cursor.y = y;
|
|
spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
|
|
|
|
crtc_flush(crtc);
|
|
request_pending(crtc, PENDING_CURSOR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct drm_crtc_funcs mdp4_crtc_funcs = {
|
|
.set_config = drm_crtc_helper_set_config,
|
|
.destroy = mdp4_crtc_destroy,
|
|
.page_flip = mdp4_crtc_page_flip,
|
|
.set_property = mdp4_crtc_set_property,
|
|
.cursor_set = mdp4_crtc_cursor_set,
|
|
.cursor_move = mdp4_crtc_cursor_move,
|
|
};
|
|
|
|
static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = {
|
|
.dpms = mdp4_crtc_dpms,
|
|
.mode_fixup = mdp4_crtc_mode_fixup,
|
|
.mode_set = mdp4_crtc_mode_set,
|
|
.prepare = mdp4_crtc_prepare,
|
|
.commit = mdp4_crtc_commit,
|
|
.mode_set_base = mdp4_crtc_mode_set_base,
|
|
.load_lut = mdp4_crtc_load_lut,
|
|
};
|
|
|
|
static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
|
|
{
|
|
struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank);
|
|
struct drm_crtc *crtc = &mdp4_crtc->base;
|
|
struct msm_drm_private *priv = crtc->dev->dev_private;
|
|
unsigned pending;
|
|
|
|
mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank);
|
|
|
|
pending = atomic_xchg(&mdp4_crtc->pending, 0);
|
|
|
|
if (pending & PENDING_FLIP) {
|
|
complete_flip(crtc, NULL);
|
|
drm_flip_work_commit(&mdp4_crtc->unref_fb_work, priv->wq);
|
|
}
|
|
|
|
if (pending & PENDING_CURSOR) {
|
|
update_cursor(crtc);
|
|
drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq);
|
|
}
|
|
}
|
|
|
|
static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
|
|
{
|
|
struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err);
|
|
struct drm_crtc *crtc = &mdp4_crtc->base;
|
|
DBG("%s: error: %08x", mdp4_crtc->name, irqstatus);
|
|
crtc_flush(crtc);
|
|
}
|
|
|
|
uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc)
|
|
{
|
|
struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
|
|
return mdp4_crtc->vblank.irqmask;
|
|
}
|
|
|
|
void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file)
|
|
{
|
|
DBG("cancel: %p", file);
|
|
complete_flip(crtc, file);
|
|
}
|
|
|
|
/* set dma config, ie. the format the encoder wants. */
|
|
void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config)
|
|
{
|
|
struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
|
|
struct mdp4_kms *mdp4_kms = get_kms(crtc);
|
|
|
|
mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config);
|
|
}
|
|
|
|
/* set interface for routing crtc->encoder: */
|
|
void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf)
|
|
{
|
|
struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
|
|
struct mdp4_kms *mdp4_kms = get_kms(crtc);
|
|
uint32_t intf_sel;
|
|
|
|
intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL);
|
|
|
|
switch (mdp4_crtc->dma) {
|
|
case DMA_P:
|
|
intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK;
|
|
intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf);
|
|
break;
|
|
case DMA_S:
|
|
intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK;
|
|
intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf);
|
|
break;
|
|
case DMA_E:
|
|
intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK;
|
|
intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf);
|
|
break;
|
|
}
|
|
|
|
if (intf == INTF_DSI_VIDEO) {
|
|
intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD;
|
|
intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO;
|
|
mdp4_crtc->mixer = 0;
|
|
} else if (intf == INTF_DSI_CMD) {
|
|
intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO;
|
|
intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD;
|
|
mdp4_crtc->mixer = 0;
|
|
} else if (intf == INTF_LCDC_DTV){
|
|
mdp4_crtc->mixer = 1;
|
|
}
|
|
|
|
blend_setup(crtc);
|
|
|
|
DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel);
|
|
|
|
mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);
|
|
}
|
|
|
|
static void set_attach(struct drm_crtc *crtc, enum mdp4_pipe pipe_id,
|
|
struct drm_plane *plane)
|
|
{
|
|
struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
|
|
|
|
BUG_ON(pipe_id >= ARRAY_SIZE(mdp4_crtc->planes));
|
|
|
|
if (mdp4_crtc->planes[pipe_id] == plane)
|
|
return;
|
|
|
|
mdp4_crtc->planes[pipe_id] = plane;
|
|
blend_setup(crtc);
|
|
if (mdp4_crtc->enabled && (plane != mdp4_crtc->plane))
|
|
crtc_flush(crtc);
|
|
}
|
|
|
|
void mdp4_crtc_attach(struct drm_crtc *crtc, struct drm_plane *plane)
|
|
{
|
|
set_attach(crtc, mdp4_plane_pipe(plane), plane);
|
|
}
|
|
|
|
void mdp4_crtc_detach(struct drm_crtc *crtc, struct drm_plane *plane)
|
|
{
|
|
/* don't actually detatch our primary plane: */
|
|
if (to_mdp4_crtc(crtc)->plane == plane)
|
|
return;
|
|
set_attach(crtc, mdp4_plane_pipe(plane), NULL);
|
|
}
|
|
|
|
static const char *dma_names[] = {
|
|
"DMA_P", "DMA_S", "DMA_E",
|
|
};
|
|
|
|
/* initialize crtc */
|
|
struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
|
|
struct drm_plane *plane, int id, int ovlp_id,
|
|
enum mdp4_dma dma_id)
|
|
{
|
|
struct drm_crtc *crtc = NULL;
|
|
struct mdp4_crtc *mdp4_crtc;
|
|
int ret;
|
|
|
|
mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL);
|
|
if (!mdp4_crtc) {
|
|
ret = -ENOMEM;
|
|
goto fail;
|
|
}
|
|
|
|
crtc = &mdp4_crtc->base;
|
|
|
|
mdp4_crtc->plane = plane;
|
|
mdp4_crtc->id = id;
|
|
|
|
mdp4_crtc->ovlp = ovlp_id;
|
|
mdp4_crtc->dma = dma_id;
|
|
|
|
mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma);
|
|
mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq;
|
|
|
|
mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma);
|
|
mdp4_crtc->err.irq = mdp4_crtc_err_irq;
|
|
|
|
snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d",
|
|
dma_names[dma_id], ovlp_id);
|
|
|
|
spin_lock_init(&mdp4_crtc->cursor.lock);
|
|
|
|
ret = drm_flip_work_init(&mdp4_crtc->unref_fb_work, 16,
|
|
"unref fb", unref_fb_worker);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
ret = drm_flip_work_init(&mdp4_crtc->unref_cursor_work, 64,
|
|
"unref cursor", unref_cursor_worker);
|
|
|
|
INIT_FENCE_CB(&mdp4_crtc->pageflip_cb, pageflip_cb);
|
|
|
|
drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp4_crtc_funcs);
|
|
drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs);
|
|
|
|
mdp4_plane_install_properties(mdp4_crtc->plane, &crtc->base);
|
|
|
|
return crtc;
|
|
|
|
fail:
|
|
if (crtc)
|
|
mdp4_crtc_destroy(crtc);
|
|
|
|
return ERR_PTR(ret);
|
|
}
|