forked from Minki/linux
387720c938
Since everybody copied my own mistake from the DT binding example, let's address all the offenders in one swift go. Most of them got the CPU interface size wrong (4kB, while it should be 8kB), except for both keystone platforms which got the control interface wrong (4kB instead of 8kB). In a few cases where I knew for sure what implementation was used, I've added the "arm,gic-400" compatible string. I'm 99% sure that this is what everyone is using, but short of having the TRM for all the other SoCs, I've left them alone. Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
453 lines
11 KiB
Plaintext
453 lines
11 KiB
Plaintext
/*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/rk1108-cru.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "rockchip,rk1108";
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@f00 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pdma: pdma@102a0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x102a0000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-broken-no-flushp;
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clocks = <&cru ACLK_DMAC>;
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clock-names = "apb_pclk";
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};
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};
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bus_intmem@10080000 {
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compatible = "mmio-sram";
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reg = <0x10080000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x10080000 0x2000>;
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};
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uart2: serial@10210000 {
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compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
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reg = <0x10210000 0x100>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2m0_xfer>;
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status = "disabled";
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};
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uart1: serial@10220000 {
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compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
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reg = <0x10220000 0x100>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer>;
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status = "disabled";
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};
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uart0: serial@10230000 {
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compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
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reg = <0x10230000 0x100>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
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status = "disabled";
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};
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grf: syscon@10300000 {
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compatible = "rockchip,rk1108-grf", "syscon";
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reg = <0x10300000 0x1000>;
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};
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pmugrf: syscon@20060000 {
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compatible = "rockchip,rk1108-pmugrf", "syscon";
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reg = <0x20060000 0x1000>;
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};
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cru: clock-controller@20200000 {
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compatible = "rockchip,rk1108-cru";
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reg = <0x20200000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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emmc: dwmmc@30110000 {
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compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
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<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x30110000 0x4000>;
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status = "disabled";
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};
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sdio: dwmmc@30120000 {
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compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
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<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x30120000 0x4000>;
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status = "disabled";
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};
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sdmmc: dwmmc@30130000 {
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compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 100000000>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
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<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x30130000 0x4000>;
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status = "disabled";
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};
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gic: interrupt-controller@32010000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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reg = <0x32011000 0x1000>,
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<0x32012000 0x2000>,
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<0x32014000 0x2000>,
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<0x32016000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk1108-pinctrl";
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rockchip,grf = <&grf>;
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rockchip,pmu = <&pmugrf>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio0@20030000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20030000 0x100>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio1@10310000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x10310000 0x100>;
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio2@10320000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x10320000 0x100>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio3@10330000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x10330000 0x100>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pcfg_pull_up: pcfg-pull-up {
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bias-pull-up;
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};
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pcfg_pull_down: pcfg-pull-down {
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bias-pull-down;
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};
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pcfg_pull_none: pcfg-pull-none {
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bias-disable;
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};
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pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
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drive-strength = <8>;
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};
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pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
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drive-strength = <12>;
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};
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pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
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bias-pull-up;
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drive-strength = <8>;
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};
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pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
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drive-strength = <4>;
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};
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pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
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bias-pull-up;
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drive-strength = <4>;
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};
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pcfg_output_high: pcfg-output-high {
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output-high;
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};
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pcfg_output_low: pcfg-output-low {
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output-low;
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};
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pcfg_input_high: pcfg-input-high {
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bias-pull-up;
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input-enable;
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};
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i2c1 {
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i2c1_xfer: i2c1-xfer {
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rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
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<2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
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};
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};
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i2c2m1 {
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i2c2m1_xfer: i2c2m1-xfer {
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rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
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<0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
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};
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i2c2m1_gpio: i2c2m1-gpio {
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rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
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<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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i2c2m05v {
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i2c2m05v_xfer: i2c2m05v-xfer {
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rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
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<1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
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};
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i2c2m05v_gpio: i2c2m05v-gpio {
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rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
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<1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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i2c3 {
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i2c3_xfer: i2c3-xfer {
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rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
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<0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
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};
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};
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sdmmc {
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sdmmc_clk: sdmmc-clk {
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rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
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};
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sdmmc_cmd: sdmmc-cmd {
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rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
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};
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sdmmc_cd: sdmmc-cd {
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rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
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};
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sdmmc_bus1: sdmmc-bus1 {
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rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
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};
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sdmmc_bus4: sdmmc-bus4 {
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rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
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<3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
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<3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
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<3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
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};
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};
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uart0 {
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uart0_xfer: uart0-xfer {
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rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
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<3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart0_cts: uart0-cts {
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rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart0_rts: uart0-rts {
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rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart0_rts_gpio: uart0-rts-gpio {
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rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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uart1 {
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uart1_xfer: uart1-xfer {
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rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
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<1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart1_cts: uart1-cts {
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rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart1_rts: uart1-rts {
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rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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uart2m0 {
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uart2m0_xfer: uart2m0-xfer {
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rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
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<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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uart2m1 {
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uart2m1_xfer: uart2m1-xfer {
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rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
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<3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
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};
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};
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uart2_5v {
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uart2_5v_cts: uart2_5v-cts {
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rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart2_5v_rts: uart2_5v-rts {
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rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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};
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};
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