f169e5ee5f
Even though every switch model has a different way to access the VTU Data bits, the base implementation of the VTU GetNext operation remains the same: wait, write the first VID to iterate from, start the operation, and read the next VID. Move this generic implementation into global1_vtu.c and abstract the handling of the start VID (similarly to the ATU GetNext implementation), before introducing a new chip operation for specific chips. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
155 lines
3.4 KiB
C
155 lines
3.4 KiB
C
/*
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* Marvell 88E6xxx VLAN [Spanning Tree] Translation Unit (VTU [STU]) support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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* Copyright (c) 2015 CMC Electronics, Inc.
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* Copyright (c) 2017 Savoir-faire Linux, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "mv88e6xxx.h"
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#include "global1.h"
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/* Offset 0x02: VTU FID Register */
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int mv88e6xxx_g1_vtu_fid_read(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
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if (err)
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return err;
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entry->fid = val & GLOBAL_VTU_FID_MASK;
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return 0;
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}
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int mv88e6xxx_g1_vtu_fid_write(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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u16 val = entry->fid & GLOBAL_VTU_FID_MASK;
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return mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, val);
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}
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/* Offset 0x03: VTU SID Register */
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int mv88e6xxx_g1_vtu_sid_read(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
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if (err)
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return err;
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entry->sid = val & GLOBAL_VTU_SID_MASK;
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return 0;
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}
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int mv88e6xxx_g1_vtu_sid_write(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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u16 val = entry->sid & GLOBAL_VTU_SID_MASK;
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return mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, val);
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}
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/* Offset 0x05: VTU Operation Register */
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int mv88e6xxx_g1_vtu_op_wait(struct mv88e6xxx_chip *chip)
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{
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return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
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}
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int mv88e6xxx_g1_vtu_op(struct mv88e6xxx_chip *chip, u16 op)
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{
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int err;
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err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
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if (err)
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return err;
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return mv88e6xxx_g1_vtu_op_wait(chip);
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}
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/* Offset 0x06: VTU VID Register */
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int mv88e6xxx_g1_vtu_vid_read(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
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if (err)
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return err;
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entry->vid = val & 0xfff;
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entry->valid = !!(val & GLOBAL_VTU_VID_VALID);
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return 0;
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}
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int mv88e6xxx_g1_vtu_vid_write(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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u16 val = entry->vid & 0xfff;
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if (entry->valid)
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val |= GLOBAL_VTU_VID_VALID;
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return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, val);
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}
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/* VLAN Translation Unit Operations */
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int mv88e6xxx_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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int err;
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err = mv88e6xxx_g1_vtu_op_wait(chip);
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if (err)
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return err;
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/* To get the next higher active VID, the VTU GetNext operation can be
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* started again without setting the VID registers since it already
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* contains the last VID.
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*
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* To save a few hardware accesses and abstract this to the caller,
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* write the VID only once, when the entry is given as invalid.
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*/
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if (!entry->valid) {
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err = mv88e6xxx_g1_vtu_vid_write(chip, entry);
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if (err)
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return err;
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}
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err = mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
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if (err)
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return err;
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return mv88e6xxx_g1_vtu_vid_read(chip, entry);
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}
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int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip)
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{
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int err;
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err = mv88e6xxx_g1_vtu_op_wait(chip);
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if (err)
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return err;
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return mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_FLUSH_ALL);
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}
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