576e0ec26b
Mapping hw counters per event config will cause ABA problems so map per event instead. v2: Discontinue starting perf counters if add fails. Make it clear what's happening with pmc_start. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Harish Kasiviswanathan <harish.kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
63 lines
2.4 KiB
C
63 lines
2.4 KiB
C
/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_DF_H__
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#define __AMDGPU_DF_H__
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struct amdgpu_df_hash_status {
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bool hash_64k;
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bool hash_2m;
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bool hash_1g;
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};
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struct amdgpu_df_funcs {
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void (*sw_init)(struct amdgpu_device *adev);
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void (*sw_fini)(struct amdgpu_device *adev);
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void (*enable_broadcast_mode)(struct amdgpu_device *adev,
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bool enable);
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u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
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u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
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void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
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bool enable);
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void (*get_clockgating_state)(struct amdgpu_device *adev,
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u32 *flags);
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void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
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bool enable);
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int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
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int counter_idx, int is_add);
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int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
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int counter_idx, int is_remove);
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void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
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int counter_idx, uint64_t *count);
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uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
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void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
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uint32_t ficadl_val, uint32_t ficadh_val);
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};
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struct amdgpu_df {
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struct amdgpu_df_hash_status hash_status;
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const struct amdgpu_df_funcs *funcs;
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};
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#endif /* __AMDGPU_DF_H__ */
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