forked from Minki/linux
ed69bdd8fd
On ARM multi-cluster systems coherency between cores running on different clusters is managed by the cache-coherent interconnect (CCI). It allows broadcasting of TLB invalidates and memory barriers and it guarantees cache coherency at system level through snooping of slave interfaces connected to it. This patch enables the basic infrastructure required in Linux to handle and programme the CCI component. Non-local variables used by the CCI management functions called by power down function calls after disabling the cache must be flushed out to main memory in advance, otherwise incoherency of those values may occur if they are sitting in the cache of some other CPU when power down functions execute. Driver code ensures that relevant data structures are flushed from inner and outer caches after the driver probe is completed. CCI slave port resources are linked to set of CPUs through bus masters phandle properties that link the interface resources to masters node in the device tree. Documentation describing the CCI DT bindings is provided with the patch. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
12 lines
316 B
Makefile
12 lines
316 B
Makefile
#
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# Makefile for the bus drivers.
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#
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obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
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obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
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# Interconnect bus driver for OMAP SoCs.
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obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
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# CCI cache coherent interconnect for ARM platforms
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obj-$(CONFIG_ARM_CCI) += arm-cci.o
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