8d897006fe
Enabling SPI controllers, which are attached to different busses
inside an SoC, may result in overlapping enumeration and cause
sysfs registration failure. Example log after enabling two
controllers on Armada 8040 SoC with same identifiers:
[ 3.740415] sysfs: cannot create duplicate filename
'/class/spi_master/spi0'
[ 3.747510] ------------[ cut here ]------------
[ 3.752145] WARNING: at fs/sysfs/dir.c:31
[...]
[ 4.002299] orion_spi: probe of f4700600.spi failed with error -17
spi-orion driver offers dedicated DT property ('cell-index'), that
allow setting unique identifiers. Recently added support for CP110-slave
HW block introduced two new SPI controllers' nodes with same ID as
ones from CP110-master.
This commit fixes the issue by assigning different 'cell-index' values
for CP110-slave SPI controllers.
Fixes: 4eef78a009 ("arm64: dts: marvell: add description for the slave
CP110 in Armada 8K")
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
250 lines
7.4 KiB
Plaintext
250 lines
7.4 KiB
Plaintext
/*
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* Copyright (C) 2016 Marvell Technology Group Ltd.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPLv2 or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Device Tree file for Marvell Armada CP110 Slave.
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*/
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/ {
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cp110-slave {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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config-space {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges = <0x0 0x0 0xf4000000 0x2000000>;
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cps_syscon0: system-controller@440000 {
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compatible = "marvell,cp110-system-controller0",
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"syscon";
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reg = <0x440000 0x1000>;
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#clock-cells = <2>;
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core-clock-output-names =
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"cps-apll", "cps-ppv2-core", "cps-eip",
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"cps-core", "cps-nand-core";
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gate-clock-output-names =
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"cps-audio", "cps-communit", "cps-nand",
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"cps-ppv2", "cps-sdio", "cps-mg-domain",
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"cps-mg-core", "cps-xor1", "cps-xor0",
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"cps-gop-dp", "none", "cps-pcie_x10",
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"cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
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"cps-sata", "cps-sata-usb", "cps-main",
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"cps-sd-mmc", "none", "none",
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"cps-slow-io", "cps-usb3h0", "cps-usb3h1",
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"cps-usb3dev", "cps-eip150", "cps-eip197";
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};
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cps_sata0: sata@540000 {
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compatible = "marvell,armada-8k-ahci";
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reg = <0x540000 0x30000>;
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interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cps_syscon0 1 15>;
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status = "disabled";
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};
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cps_usb3_0: usb3@500000 {
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compatible = "marvell,armada-8k-xhci",
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"generic-xhci";
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reg = <0x500000 0x4000>;
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dma-coherent;
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interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cps_syscon0 1 22>;
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status = "disabled";
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};
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cps_usb3_1: usb3@510000 {
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compatible = "marvell,armada-8k-xhci",
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"generic-xhci";
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reg = <0x510000 0x4000>;
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dma-coherent;
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interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cps_syscon0 1 23>;
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status = "disabled";
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};
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cps_xor0: xor@6a0000 {
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compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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reg = <0x6a0000 0x1000>,
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<0x6b0000 0x1000>;
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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clocks = <&cps_syscon0 1 8>;
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};
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cps_xor1: xor@6c0000 {
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compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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reg = <0x6c0000 0x1000>,
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<0x6d0000 0x1000>;
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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clocks = <&cps_syscon0 1 7>;
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};
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cps_spi0: spi@700600 {
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compatible = "marvell,armada-380-spi";
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reg = <0x700600 0x50>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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cell-index = <3>;
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clocks = <&cps_syscon0 1 21>;
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status = "disabled";
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};
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cps_spi1: spi@700680 {
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compatible = "marvell,armada-380-spi";
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reg = <0x700680 0x50>;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <4>;
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clocks = <&cps_syscon0 1 21>;
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status = "disabled";
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};
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cps_i2c0: i2c@701000 {
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compatible = "marvell,mv78230-i2c";
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reg = <0x701000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cps_syscon0 1 21>;
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status = "disabled";
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};
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cps_i2c1: i2c@701100 {
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compatible = "marvell,mv78230-i2c";
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reg = <0x701100 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cps_syscon0 1 21>;
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status = "disabled";
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};
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};
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cps_pcie0: pcie@f4600000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg = <0 0xf4600000 0 0x10000>,
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<0 0xfaf00000 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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bus-range = <0 0xff>;
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ranges =
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/* downstream I/O */
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<0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
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/* non-prefetchable memory */
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0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&cps_syscon0 1 13>;
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status = "disabled";
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};
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cps_pcie1: pcie@f4620000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg = <0 0xf4620000 0 0x10000>,
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<0 0xfbf00000 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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bus-range = <0 0xff>;
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ranges =
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/* downstream I/O */
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<0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
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/* non-prefetchable memory */
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0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&cps_syscon0 1 11>;
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status = "disabled";
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};
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cps_pcie2: pcie@f4640000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg = <0 0xf4640000 0 0x10000>,
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<0 0xfcf00000 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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bus-range = <0 0xff>;
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ranges =
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/* downstream I/O */
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<0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
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/* non-prefetchable memory */
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0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&cps_syscon0 1 12>;
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status = "disabled";
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};
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};
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};
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