forked from Minki/linux
e695c71892
The Power Sleep Controller (PSC) module contains specific memory-mapped registers that can be used to perform reset management using specific bits for the DSPs available on the SoC. The PSC is defined using a syscon node, and the reset functionality is defined using a child syscon reset controller node. Add this syscon reset controller node as well as the reset control data for the resets it supports for the 66AK2H SoCs. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
150 lines
3.6 KiB
Plaintext
150 lines
3.6 KiB
Plaintext
/*
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* Copyright 2013-2014 Texas Instruments, Inc.
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*
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* Keystone 2 Kepler/Hawking soc specific device tree
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/reset/ti-syscon.h>
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/ {
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compatible = "ti,k2hk", "ti,keystone";
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model = "Texas Instruments Keystone 2 Kepler/Hawking SoC";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&gic>;
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cpu@0 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <1>;
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};
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cpu@2 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <3>;
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};
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};
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soc {
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/include/ "keystone-k2hk-clocks.dtsi"
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msm_ram: msmram@0c000000 {
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compatible = "mmio-sram";
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reg = <0x0c000000 0x600000>;
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ranges = <0x0 0x0c000000 0x600000>;
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#address-cells = <1>;
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#size-cells = <1>;
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sram-bm@5f0000 {
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reg = <0x5f0000 0x8000>;
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};
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};
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psc: power-sleep-controller@02350000 {
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pscrst: reset-controller {
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compatible = "ti,k2hk-pscrst", "ti,syscon-reset";
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#reset-cells = <1>;
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ti,reset-bits = <
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0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
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0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */
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0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */
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0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */
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0xa4c 8 0xa4c 8 0x84c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 4: dsp4 */
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0xa50 8 0xa50 8 0x850 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 5: dsp5 */
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0xa54 8 0xa54 8 0x854 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 6: dsp6 */
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0xa58 8 0xa58 8 0x858 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 7: dsp7 */
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>;
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};
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};
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dspgpio0: keystone_dsp_gpio@02620240 {
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compatible = "ti,keystone-dsp-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio,syscon-dev = <&devctrl 0x240>;
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};
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dspgpio1: keystone_dsp_gpio@2620244 {
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compatible = "ti,keystone-dsp-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio,syscon-dev = <&devctrl 0x244>;
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};
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dspgpio2: keystone_dsp_gpio@2620248 {
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compatible = "ti,keystone-dsp-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio,syscon-dev = <&devctrl 0x248>;
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};
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dspgpio3: keystone_dsp_gpio@262024c {
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compatible = "ti,keystone-dsp-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio,syscon-dev = <&devctrl 0x24c>;
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};
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dspgpio4: keystone_dsp_gpio@2620250 {
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compatible = "ti,keystone-dsp-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio,syscon-dev = <&devctrl 0x250>;
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};
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dspgpio5: keystone_dsp_gpio@2620254 {
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compatible = "ti,keystone-dsp-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio,syscon-dev = <&devctrl 0x254>;
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};
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dspgpio6: keystone_dsp_gpio@2620258 {
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compatible = "ti,keystone-dsp-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio,syscon-dev = <&devctrl 0x258>;
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};
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dspgpio7: keystone_dsp_gpio@262025c {
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compatible = "ti,keystone-dsp-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio,syscon-dev = <&devctrl 0x25c>;
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};
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mdio: mdio@02090300 {
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compatible = "ti,keystone_mdio", "ti,davinci_mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x02090300 0x100>;
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status = "disabled";
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clocks = <&clkcpgmac>;
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clock-names = "fck";
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bus_freq = <2500000>;
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};
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/include/ "keystone-k2hk-netcp.dtsi"
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};
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};
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