Philip Yang 0f12a22f37 drm/amdgpu: Flush TLB after mapping for VG20+XGMI ...

For VG20 + XGMI bridge, all mappings PTEs cache in TC, this may have
stall invalid PTEs in TC because one cache line has 8 pages. Need always
flush_tlb after updating mapping.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2022-04-05 10:29:47 -04:00

66 KiB

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