597ce1723e
CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs do. In order to preserve backwards compatibility a 64-bit FPU will act like a 32-bit FPU (by accessing doubles from the least significant 32 bits of an even-odd pair of FP registers) when the Status.FR bit is zero, again just like a mips64 CPU. The standard O32 ABI is defined expecting a 32-bit FPU, however recent toolchains support use of a 64-bit FPU from an O32 MIPS32 executable. When an ELF executable is built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF header. With this patch the kernel will check the EF_MIPS_FP64 flag when executing an O32 binary, and set Status.FR accordingly. The addition of O32 64-bit FP support lessens the opportunity for optimisation in the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is introduced to allow this support to be disabled for those that don't require it. Inspired by an earlier patch by Leonid Yegoshin, but implemented more cleanly & correctly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
200 lines
4.6 KiB
C
200 lines
4.6 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 Ralf Baechle
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*/
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#ifndef _ASM_ASMMACRO_H
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#define _ASM_ASMMACRO_H
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#include <asm/hazards.h>
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#ifdef CONFIG_32BIT
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#include <asm/asmmacro-32.h>
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#endif
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#ifdef CONFIG_64BIT
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#include <asm/asmmacro-64.h>
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#endif
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#ifdef CONFIG_MIPS_MT_SMTC
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#include <asm/mipsmtregs.h>
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#endif
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#ifdef CONFIG_MIPS_MT_SMTC
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.macro local_irq_enable reg=t0
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mfc0 \reg, CP0_TCSTATUS
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ori \reg, \reg, TCSTATUS_IXMT
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xori \reg, \reg, TCSTATUS_IXMT
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mtc0 \reg, CP0_TCSTATUS
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_ehb
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.endm
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.macro local_irq_disable reg=t0
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mfc0 \reg, CP0_TCSTATUS
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ori \reg, \reg, TCSTATUS_IXMT
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mtc0 \reg, CP0_TCSTATUS
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_ehb
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.endm
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#elif defined(CONFIG_CPU_MIPSR2)
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.macro local_irq_enable reg=t0
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ei
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irq_enable_hazard
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.endm
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.macro local_irq_disable reg=t0
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di
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irq_disable_hazard
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.endm
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#else
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.macro local_irq_enable reg=t0
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mfc0 \reg, CP0_STATUS
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ori \reg, \reg, 1
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mtc0 \reg, CP0_STATUS
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irq_enable_hazard
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.endm
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.macro local_irq_disable reg=t0
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mfc0 \reg, CP0_STATUS
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ori \reg, \reg, 1
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xori \reg, \reg, 1
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mtc0 \reg, CP0_STATUS
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irq_disable_hazard
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.endm
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#endif /* CONFIG_MIPS_MT_SMTC */
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.macro fpu_save_16even thread tmp=t0
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cfc1 \tmp, fcr31
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sdc1 $f0, THREAD_FPR0(\thread)
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sdc1 $f2, THREAD_FPR2(\thread)
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sdc1 $f4, THREAD_FPR4(\thread)
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sdc1 $f6, THREAD_FPR6(\thread)
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sdc1 $f8, THREAD_FPR8(\thread)
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sdc1 $f10, THREAD_FPR10(\thread)
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sdc1 $f12, THREAD_FPR12(\thread)
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sdc1 $f14, THREAD_FPR14(\thread)
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sdc1 $f16, THREAD_FPR16(\thread)
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sdc1 $f18, THREAD_FPR18(\thread)
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sdc1 $f20, THREAD_FPR20(\thread)
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sdc1 $f22, THREAD_FPR22(\thread)
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sdc1 $f24, THREAD_FPR24(\thread)
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sdc1 $f26, THREAD_FPR26(\thread)
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sdc1 $f28, THREAD_FPR28(\thread)
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sdc1 $f30, THREAD_FPR30(\thread)
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sw \tmp, THREAD_FCR31(\thread)
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.endm
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.macro fpu_save_16odd thread
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.set push
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.set mips64r2
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sdc1 $f1, THREAD_FPR1(\thread)
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sdc1 $f3, THREAD_FPR3(\thread)
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sdc1 $f5, THREAD_FPR5(\thread)
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sdc1 $f7, THREAD_FPR7(\thread)
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sdc1 $f9, THREAD_FPR9(\thread)
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sdc1 $f11, THREAD_FPR11(\thread)
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sdc1 $f13, THREAD_FPR13(\thread)
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sdc1 $f15, THREAD_FPR15(\thread)
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sdc1 $f17, THREAD_FPR17(\thread)
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sdc1 $f19, THREAD_FPR19(\thread)
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sdc1 $f21, THREAD_FPR21(\thread)
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sdc1 $f23, THREAD_FPR23(\thread)
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sdc1 $f25, THREAD_FPR25(\thread)
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sdc1 $f27, THREAD_FPR27(\thread)
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sdc1 $f29, THREAD_FPR29(\thread)
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sdc1 $f31, THREAD_FPR31(\thread)
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.set pop
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.endm
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.macro fpu_save_double thread status tmp
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#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2)
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sll \tmp, \status, 5
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bgez \tmp, 10f
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fpu_save_16odd \thread
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10:
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#endif
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fpu_save_16even \thread \tmp
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.endm
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.macro fpu_restore_16even thread tmp=t0
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lw \tmp, THREAD_FCR31(\thread)
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ldc1 $f0, THREAD_FPR0(\thread)
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ldc1 $f2, THREAD_FPR2(\thread)
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ldc1 $f4, THREAD_FPR4(\thread)
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ldc1 $f6, THREAD_FPR6(\thread)
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ldc1 $f8, THREAD_FPR8(\thread)
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ldc1 $f10, THREAD_FPR10(\thread)
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ldc1 $f12, THREAD_FPR12(\thread)
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ldc1 $f14, THREAD_FPR14(\thread)
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ldc1 $f16, THREAD_FPR16(\thread)
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ldc1 $f18, THREAD_FPR18(\thread)
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ldc1 $f20, THREAD_FPR20(\thread)
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ldc1 $f22, THREAD_FPR22(\thread)
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ldc1 $f24, THREAD_FPR24(\thread)
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ldc1 $f26, THREAD_FPR26(\thread)
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ldc1 $f28, THREAD_FPR28(\thread)
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ldc1 $f30, THREAD_FPR30(\thread)
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ctc1 \tmp, fcr31
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.endm
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.macro fpu_restore_16odd thread
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.set push
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.set mips64r2
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ldc1 $f1, THREAD_FPR1(\thread)
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ldc1 $f3, THREAD_FPR3(\thread)
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ldc1 $f5, THREAD_FPR5(\thread)
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ldc1 $f7, THREAD_FPR7(\thread)
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ldc1 $f9, THREAD_FPR9(\thread)
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ldc1 $f11, THREAD_FPR11(\thread)
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ldc1 $f13, THREAD_FPR13(\thread)
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ldc1 $f15, THREAD_FPR15(\thread)
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ldc1 $f17, THREAD_FPR17(\thread)
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ldc1 $f19, THREAD_FPR19(\thread)
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ldc1 $f21, THREAD_FPR21(\thread)
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ldc1 $f23, THREAD_FPR23(\thread)
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ldc1 $f25, THREAD_FPR25(\thread)
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ldc1 $f27, THREAD_FPR27(\thread)
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ldc1 $f29, THREAD_FPR29(\thread)
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ldc1 $f31, THREAD_FPR31(\thread)
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.set pop
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.endm
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.macro fpu_restore_double thread status tmp
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#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2)
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sll \tmp, \status, 5
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bgez \tmp, 10f # 16 register mode?
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fpu_restore_16odd \thread
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10:
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#endif
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fpu_restore_16even \thread \tmp
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.endm
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/*
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* Temporary until all gas have MT ASE support
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*/
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.macro DMT reg=0
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.word 0x41600bc1 | (\reg << 16)
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.endm
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.macro EMT reg=0
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.word 0x41600be1 | (\reg << 16)
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.endm
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.macro DVPE reg=0
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.word 0x41600001 | (\reg << 16)
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.endm
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.macro EVPE reg=0
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.word 0x41600021 | (\reg << 16)
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.endm
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.macro MFTR rt=0, rd=0, u=0, sel=0
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.word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
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.endm
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.macro MTTR rt=0, rd=0, u=0, sel=0
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.word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
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.endm
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#endif /* _ASM_ASMMACRO_H */
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