e8dd920776
Add a driver to control the output of the sample clock generator found in the axg audio clock controller. The goal of this driver is to coherently control the phase provided to the different element using the sample clock generator. This simplify the usage of the sample clock generator a lot, without comprising the ability of the SoC. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
21 lines
388 B
C
21 lines
388 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#ifndef __MESON_CLKC_AUDIO_H
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#define __MESON_CLKC_AUDIO_H
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#include "clkc.h"
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struct meson_clk_triphase_data {
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struct parm ph0;
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struct parm ph1;
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struct parm ph2;
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};
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extern const struct clk_ops meson_clk_triphase_ops;
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#endif /* __MESON_CLKC_AUDIO_H */
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