- "genirq: Introduce generic irq migration for cpu hotunplugged" patch merged from tip/irq/for-arm to allow the arm64-specific part to be upstreamed via the arm64 tree - CPU feature detection reworked to cope with heterogeneous systems where CPUs may not have exactly the same features. The features reported by the kernel via internal data structures or ELF_HWCAP are delayed until all the CPUs are up (and before user space starts) - Support for 16KB pages, with the additional bonus of a 36-bit VA space, though the latter only depending on EXPERT - Implement native {relaxed, acquire, release} atomics for arm64 - New ASID allocation algorithm which avoids IPI on roll-over, together with TLB invalidation optimisations (using local vs global where feasible) - KASan support for arm64 - EFI_STUB clean-up and isolation for the kernel proper (required by KASan) - copy_{to,from,in}_user optimisations (sharing the memcpy template) - perf: moving arm64 to the arm32/64 shared PMU framework - L1_CACHE_BYTES increased to 128 to accommodate Cavium hardware - Support for the contiguous PTE hint on kernel mapping (16 consecutive entries may be able to use a single TLB entry) - Generic CONFIG_HZ now used on arm64 - defconfig updates -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWOkmIAAoJEGvWsS0AyF7x4GgQAINU3NePjFFvWZNCkqobeH9+ jFKwtXamIudhTSdnXNXyYWmtRL9Krg3qI4zDQf68dvDFAZAze2kVuOi1yPpCbpFZ /j/afNyQc7+PoyqRAzmT+EMPZlcuOA84Prrl1r3QWZ58QaFeVk/6ZxrHunTHxN0x mR9PIXfWx73MTo+UnG8FChkmEY6LmV4XpemgTaMR9FqFhdT51OZSxDDAYXOTm4JW a5HdN9OWjjJ2rhLlFEaC7tszG9B5doHdy2tr5ge/YERVJzIPDogHkMe8ZhfAJc+x SQU5tKN6Pg4MOi+dLhxlk0/mKCvHLiEQ5KVREJnt8GxupAR54Bat+DQ+rP9cSnpq dRQTcARIOyy9LGgy+ROAsSo+NiyM5WuJ0/WJUYKmgWTJOfczRYoZv6TMKlwNOUYb tGLCZHhKPM3yBHJlWbQykl3xmSuudxCMmjlZzg7B+MVfTP6uo0CRSPmYl+v67q+J bBw/Z2RYXWYGnvlc6OfbMeImI6prXeE36+5ytyJFga0m+IqcTzRGzjcLxKEvdbiU pr8n9i+hV9iSsT/UwukXZ8ay6zH7PrTLzILWQlieutfXlvha7MYeGxnkbLmdYcfe GCj374io5cdImHcVKmfhnOMlFOLuOHphl9cmsd/O2LmCIqBj9BIeNH2Om8mHVK2F YHczMdpESlJApE7kUc1e =3six -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Catalin Marinas: - "genirq: Introduce generic irq migration for cpu hotunplugged" patch merged from tip/irq/for-arm to allow the arm64-specific part to be upstreamed via the arm64 tree - CPU feature detection reworked to cope with heterogeneous systems where CPUs may not have exactly the same features. The features reported by the kernel via internal data structures or ELF_HWCAP are delayed until all the CPUs are up (and before user space starts) - Support for 16KB pages, with the additional bonus of a 36-bit VA space, though the latter only depending on EXPERT - Implement native {relaxed, acquire, release} atomics for arm64 - New ASID allocation algorithm which avoids IPI on roll-over, together with TLB invalidation optimisations (using local vs global where feasible) - KASan support for arm64 - EFI_STUB clean-up and isolation for the kernel proper (required by KASan) - copy_{to,from,in}_user optimisations (sharing the memcpy template) - perf: moving arm64 to the arm32/64 shared PMU framework - L1_CACHE_BYTES increased to 128 to accommodate Cavium hardware - Support for the contiguous PTE hint on kernel mapping (16 consecutive entries may be able to use a single TLB entry) - Generic CONFIG_HZ now used on arm64 - defconfig updates * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (91 commits) arm64/efi: fix libstub build under CONFIG_MODVERSIONS ARM64: Enable multi-core scheduler support by default arm64/efi: move arm64 specific stub C code to libstub arm64: page-align sections for DEBUG_RODATA arm64: Fix build with CONFIG_ZONE_DMA=n arm64: Fix compat register mappings arm64: Increase the max granular size arm64: remove bogus TASK_SIZE_64 check arm64: make Timer Interrupt Frequency selectable arm64/mm: use PAGE_ALIGNED instead of IS_ALIGNED arm64: cachetype: fix definitions of ICACHEF_* flags arm64: cpufeature: declare enable_cpu_capabilities as static genirq: Make the cpuhotplug migration code less noisy arm64: Constify hwcap name string arrays arm64/kvm: Make use of the system wide safe values arm64/debug: Make use of the system wide safe value arm64: Move FP/ASIMD hwcap handling to common code arm64/HWCAP: Use system wide safe values arm64/capabilities: Make use of system wide safe value arm64: Delay cpu feature capability checks ...
143 lines
4.1 KiB
C
143 lines
4.1 KiB
C
#include <linux/percpu.h>
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#include <linux/slab.h>
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#include <asm/cacheflush.h>
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#include <asm/debug-monitors.h>
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#include <asm/pgtable.h>
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#include <asm/memory.h>
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#include <asm/mmu_context.h>
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#include <asm/smp_plat.h>
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#include <asm/suspend.h>
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#include <asm/tlbflush.h>
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extern int __cpu_suspend_enter(unsigned long arg, int (*fn)(unsigned long));
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/*
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* This is called by __cpu_suspend_enter() to save the state, and do whatever
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* flushing is required to ensure that when the CPU goes to sleep we have
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* the necessary data available when the caches are not searched.
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*
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* ptr: CPU context virtual address
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* save_ptr: address of the location where the context physical address
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* must be saved
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*/
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void notrace __cpu_suspend_save(struct cpu_suspend_ctx *ptr,
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phys_addr_t *save_ptr)
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{
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*save_ptr = virt_to_phys(ptr);
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cpu_do_suspend(ptr);
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/*
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* Only flush the context that must be retrieved with the MMU
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* off. VA primitives ensure the flush is applied to all
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* cache levels so context is pushed to DRAM.
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*/
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__flush_dcache_area(ptr, sizeof(*ptr));
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__flush_dcache_area(save_ptr, sizeof(*save_ptr));
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}
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/*
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* This hook is provided so that cpu_suspend code can restore HW
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* breakpoints as early as possible in the resume path, before reenabling
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* debug exceptions. Code cannot be run from a CPU PM notifier since by the
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* time the notifier runs debug exceptions might have been enabled already,
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* with HW breakpoints registers content still in an unknown state.
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*/
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void (*hw_breakpoint_restore)(void *);
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void __init cpu_suspend_set_dbg_restorer(void (*hw_bp_restore)(void *))
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{
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/* Prevent multiple restore hook initializations */
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if (WARN_ON(hw_breakpoint_restore))
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return;
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hw_breakpoint_restore = hw_bp_restore;
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}
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/*
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* cpu_suspend
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*
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* arg: argument to pass to the finisher function
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* fn: finisher function pointer
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*
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*/
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int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
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{
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struct mm_struct *mm = current->active_mm;
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int ret;
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unsigned long flags;
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/*
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* From this point debug exceptions are disabled to prevent
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* updates to mdscr register (saved and restored along with
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* general purpose registers) from kernel debuggers.
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*/
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local_dbg_save(flags);
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/*
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* mm context saved on the stack, it will be restored when
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* the cpu comes out of reset through the identity mapped
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* page tables, so that the thread address space is properly
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* set-up on function return.
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*/
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ret = __cpu_suspend_enter(arg, fn);
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if (ret == 0) {
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/*
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* We are resuming from reset with TTBR0_EL1 set to the
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* idmap to enable the MMU; set the TTBR0 to the reserved
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* page tables to prevent speculative TLB allocations, flush
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* the local tlb and set the default tcr_el1.t0sz so that
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* the TTBR0 address space set-up is properly restored.
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* If the current active_mm != &init_mm we entered cpu_suspend
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* with mappings in TTBR0 that must be restored, so we switch
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* them back to complete the address space configuration
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* restoration before returning.
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*/
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cpu_set_reserved_ttbr0();
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local_flush_tlb_all();
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cpu_set_default_tcr_t0sz();
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if (mm != &init_mm)
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cpu_switch_mm(mm->pgd, mm);
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/*
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* Restore per-cpu offset before any kernel
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* subsystem relying on it has a chance to run.
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*/
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set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
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/*
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* Restore HW breakpoint registers to sane values
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* before debug exceptions are possibly reenabled
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* through local_dbg_restore.
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*/
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if (hw_breakpoint_restore)
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hw_breakpoint_restore(NULL);
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}
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/*
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* Restore pstate flags. OS lock and mdscr have been already
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* restored, so from this point onwards, debugging is fully
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* renabled if it was enabled when core started shutdown.
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*/
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local_dbg_restore(flags);
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return ret;
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}
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struct sleep_save_sp sleep_save_sp;
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static int __init cpu_suspend_init(void)
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{
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void *ctx_ptr;
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/* ctx_ptr is an array of physical addresses */
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ctx_ptr = kcalloc(mpidr_hash_size(), sizeof(phys_addr_t), GFP_KERNEL);
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if (WARN_ON(!ctx_ptr))
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return -ENOMEM;
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sleep_save_sp.save_ptr_stash = ctx_ptr;
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sleep_save_sp.save_ptr_stash_phys = virt_to_phys(ctx_ptr);
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__flush_dcache_area(&sleep_save_sp, sizeof(struct sleep_save_sp));
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return 0;
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}
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early_initcall(cpu_suspend_init);
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