forked from Minki/linux
a04b07c0fc
This patch reworks wake-up interrupt handling in pinctrl-exynos driver,
so each pin bank, which provides wake-up interrupts, has its own IRQ
domain.
Information about whether given pin bank provides wake-up interrupts,
how many and whether they are separate or muxed are parsed from device
tree.
It gives following advantages:
- interrupts can be specified in device tree in a more readable way,
e.g. :
device {
/* ... */
interrupt-parent = <&gpx2>;
interrupts = <4 0>;
/* ... */
};
- the amount and layout of interrupts is not hardcoded in the code
anymore, but defined in SoC-specific structure
- bank and pin of each wake-up interrupt can be easily identified, to
allow operations, such as setting the pin to EINT function, from
irq_set_type() callback
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
109 lines
3.0 KiB
C
109 lines
3.0 KiB
C
/*
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* Exynos specific definitions for Samsung pinctrl and gpiolib driver.
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2012 Linaro Ltd
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* http://www.linaro.org
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*
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* This file contains the Exynos specific definitions for the Samsung
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* pinctrl/gpiolib interface drivers.
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*
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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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/* External GPIO and wakeup interrupt related definitions */
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#define EXYNOS_GPIO_ECON_OFFSET 0x700
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#define EXYNOS_GPIO_EMASK_OFFSET 0x900
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#define EXYNOS_GPIO_EPEND_OFFSET 0xA00
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#define EXYNOS_WKUP_ECON_OFFSET 0xE00
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#define EXYNOS_WKUP_EMASK_OFFSET 0xF00
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#define EXYNOS_WKUP_EPEND_OFFSET 0xF40
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#define EXYNOS_SVC_OFFSET 0xB08
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#define EXYNOS_EINT_FUNC 0xF
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/* helpers to access interrupt service register */
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#define EXYNOS_SVC_GROUP_SHIFT 3
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#define EXYNOS_SVC_GROUP_MASK 0x1f
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#define EXYNOS_SVC_NUM_MASK 7
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#define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \
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EXYNOS_SVC_GROUP_MASK)
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/* Exynos specific external interrupt trigger types */
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#define EXYNOS_EINT_LEVEL_LOW 0
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#define EXYNOS_EINT_LEVEL_HIGH 1
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#define EXYNOS_EINT_EDGE_FALLING 2
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#define EXYNOS_EINT_EDGE_RISING 3
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#define EXYNOS_EINT_EDGE_BOTH 4
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#define EXYNOS_EINT_CON_MASK 0xF
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#define EXYNOS_EINT_CON_LEN 4
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#define EXYNOS_EINT_MAX_PER_BANK 8
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#define EXYNOS_EINT_NR_WKUP_EINT
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#define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \
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{ \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.func_width = 4, \
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.pud_width = 2, \
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.drv_width = 2, \
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.conpdn_width = 2, \
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.pudpdn_width = 2, \
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.eint_type = EINT_TYPE_NONE, \
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.name = id \
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}
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#define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \
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{ \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.func_width = 4, \
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.pud_width = 2, \
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.drv_width = 2, \
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.conpdn_width = 2, \
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.pudpdn_width = 2, \
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.eint_type = EINT_TYPE_GPIO, \
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.eint_offset = offs, \
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.name = id \
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}
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#define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \
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{ \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.func_width = 4, \
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.pud_width = 2, \
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.drv_width = 2, \
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.eint_type = EINT_TYPE_WKUP, \
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.eint_offset = offs, \
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.name = id \
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}
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/**
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* struct exynos_weint_data: irq specific data for all the wakeup interrupts
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* generated by the external wakeup interrupt controller.
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* @irq: interrupt number within the domain.
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* @bank: bank responsible for this interrupt
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*/
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struct exynos_weint_data {
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unsigned int irq;
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struct samsung_pin_bank *bank;
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};
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/**
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* struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts
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* generated by the external wakeup interrupt controller.
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* @nr_banks: count of banks being part of the mux
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* @banks: array of banks being part of the mux
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*/
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struct exynos_muxed_weint_data {
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unsigned int nr_banks;
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struct samsung_pin_bank *banks[];
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};
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