forked from Minki/linux
f28d7de6bd
DT-enabled Marvell Kirkwood and Dove SoCs make use of an irqchip driver. As expected for irqchip drivers, it uses a C-style interrupt handler and therefore selects MULTI_IRQ_HANDLER. Now, compiling a kernel with both non-DT and DT support enabled, selecting MULTI_IRQ_HANDLER will break ASM irq handler used by non-DT boards. Therefore, we provide a C-style irq handler even for non-DT boards, if MULTI_IRQ_HANDLER is set. By installing the C-style irq handler in orion_irq_init this is transparent to all non-DT board files. While the regression report was filed on Marvell Kirkwood, also Marvell Dove non-DT boards are affected and fixed by this patch. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Reported-by: Ian Campbell <ijc@hellion.org.uk> Cc: <stable@vger.kernel.org> # v3.12+ Fixes:2326f04321("ARM: kirkwood: convert to DT irqchip and clocksource") Fixes:f07d73e33d("ARM: dove: convert to DT irqchip and clocksource") Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
118 lines
2.8 KiB
C
118 lines
2.8 KiB
C
/*
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* arch/arm/plat-orion/irq.c
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*
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* Marvell Orion SoC IRQ handling.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/exception.h>
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#include <plat/irq.h>
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#include <plat/orion-gpio.h>
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#include <mach/bridge-regs.h>
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#ifdef CONFIG_MULTI_IRQ_HANDLER
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/*
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* Compiling with both non-DT and DT support enabled, will
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* break asm irq handler used by non-DT boards. Therefore,
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* we provide a C-style irq handler even for non-DT boards,
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* if MULTI_IRQ_HANDLER is set.
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*
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* Notes:
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* - this is prepared for Kirkwood and Dove only, update
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* accordingly if you add Orion5x or MV78x00.
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* - Orion5x uses different macro names and has only one
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* set of CAUSE/MASK registers.
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* - MV78x00 uses the same macro names but has a third
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* set of CAUSE/MASK registers.
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*
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*/
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static void __iomem *orion_irq_base = IRQ_VIRT_BASE;
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asmlinkage void
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__exception_irq_entry orion_legacy_handle_irq(struct pt_regs *regs)
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{
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u32 stat;
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stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_LOW_OFF);
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stat &= readl_relaxed(orion_irq_base + IRQ_MASK_LOW_OFF);
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if (stat) {
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unsigned int hwirq = __fls(stat);
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handle_IRQ(hwirq, regs);
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return;
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}
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stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_HIGH_OFF);
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stat &= readl_relaxed(orion_irq_base + IRQ_MASK_HIGH_OFF);
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if (stat) {
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unsigned int hwirq = 32 + __fls(stat);
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handle_IRQ(hwirq, regs);
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return;
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}
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}
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#endif
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void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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/*
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* Mask all interrupts initially.
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*/
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writel(0, maskaddr);
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gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr,
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handle_level_irq);
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ct = gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
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#ifdef CONFIG_MULTI_IRQ_HANDLER
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set_handle_irq(orion_legacy_handle_irq);
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#endif
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}
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#ifdef CONFIG_OF
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static int __init orion_add_irq_domain(struct device_node *np,
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struct device_node *interrupt_parent)
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{
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int i = 0;
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void __iomem *base;
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do {
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base = of_iomap(np, i);
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if (base) {
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orion_irq_init(i * 32, base + 0x04);
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i++;
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}
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} while (base);
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irq_domain_add_legacy(np, i * 32, 0, 0,
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&irq_domain_simple_ops, NULL);
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return 0;
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}
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static const struct of_device_id orion_irq_match[] = {
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{ .compatible = "marvell,orion-intc",
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.data = orion_add_irq_domain, },
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{},
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};
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void __init orion_dt_init_irq(void)
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{
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of_irq_init(orion_irq_match);
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}
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#endif
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