forked from Minki/linux
3f65ce4d14
The attached patches provides part 5 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
546 lines
15 KiB
C
546 lines
15 KiB
C
/*
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* arch/xtensa/mm/mmu.c
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*
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* Logic that manipulates the Xtensa MMU. Derived from MIPS.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2003 Tensilica Inc.
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*
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* Joe Taylor
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* Chris Zankel <chris@zankel.net>
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* Marc Gauthier
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*/
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#include <linux/mm.h>
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#include <asm/processor.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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#include <asm/system.h>
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#include <asm/cacheflush.h>
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static inline void __flush_itlb_all (void)
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{
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int way, index;
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for (way = 0; way < XCHAL_ITLB_ARF_WAYS; way++) {
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for (index = 0; index < ITLB_ENTRIES_PER_ARF_WAY; index++) {
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int entry = way + (index << PAGE_SHIFT);
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invalidate_itlb_entry_no_isync (entry);
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}
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}
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asm volatile ("isync\n");
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}
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static inline void __flush_dtlb_all (void)
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{
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int way, index;
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for (way = 0; way < XCHAL_DTLB_ARF_WAYS; way++) {
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for (index = 0; index < DTLB_ENTRIES_PER_ARF_WAY; index++) {
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int entry = way + (index << PAGE_SHIFT);
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invalidate_dtlb_entry_no_isync (entry);
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}
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}
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asm volatile ("isync\n");
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}
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void flush_tlb_all (void)
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{
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__flush_itlb_all();
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__flush_dtlb_all();
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}
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/* If mm is current, we simply assign the current task a new ASID, thus,
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* invalidating all previous tlb entries. If mm is someone else's user mapping,
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* wie invalidate the context, thus, when that user mapping is swapped in,
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* a new context will be assigned to it.
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*/
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void flush_tlb_mm(struct mm_struct *mm)
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{
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#if 0
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printk("[tlbmm<%lx>]\n", (unsigned long)mm->context);
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#endif
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if (mm == current->active_mm) {
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int flags;
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local_save_flags(flags);
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get_new_mmu_context(mm, asid_cache);
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set_rasid_register(ASID_INSERT(mm->context));
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local_irq_restore(flags);
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}
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else
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mm->context = 0;
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}
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void flush_tlb_range (struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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unsigned long flags;
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if (mm->context == NO_CONTEXT)
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return;
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#if 0
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printk("[tlbrange<%02lx,%08lx,%08lx>]\n",
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(unsigned long)mm->context, start, end);
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#endif
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local_save_flags(flags);
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if (end-start + (PAGE_SIZE-1) <= SMALLEST_NTLB_ENTRIES << PAGE_SHIFT) {
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int oldpid = get_rasid_register();
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set_rasid_register (ASID_INSERT(mm->context));
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start &= PAGE_MASK;
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if (vma->vm_flags & VM_EXEC)
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while(start < end) {
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invalidate_itlb_mapping(start);
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invalidate_dtlb_mapping(start);
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start += PAGE_SIZE;
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}
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else
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while(start < end) {
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invalidate_dtlb_mapping(start);
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start += PAGE_SIZE;
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}
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set_rasid_register(oldpid);
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} else {
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get_new_mmu_context(mm, asid_cache);
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if (mm == current->active_mm)
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set_rasid_register(ASID_INSERT(mm->context));
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}
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local_irq_restore(flags);
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}
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void flush_tlb_page (struct vm_area_struct *vma, unsigned long page)
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{
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struct mm_struct* mm = vma->vm_mm;
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unsigned long flags;
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int oldpid;
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#if 0
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printk("[tlbpage<%02lx,%08lx>]\n",
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(unsigned long)mm->context, page);
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#endif
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if(mm->context == NO_CONTEXT)
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return;
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local_save_flags(flags);
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oldpid = get_rasid_register();
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if (vma->vm_flags & VM_EXEC)
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invalidate_itlb_mapping(page);
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invalidate_dtlb_mapping(page);
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set_rasid_register(oldpid);
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local_irq_restore(flags);
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#if 0
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flush_tlb_all();
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return;
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#endif
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}
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#ifdef DEBUG_TLB
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#define USE_ITLB 0
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#define USE_DTLB 1
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struct way_config_t {
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int indicies;
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int indicies_log2;
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int pgsz_log2;
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int arf;
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};
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static struct way_config_t itlb[XCHAL_ITLB_WAYS] =
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{
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{ XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ENTRIES),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ENTRIES_LOG2),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, PAGESZ_LOG2_MIN),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ARF)
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},
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{ XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ENTRIES),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ENTRIES_LOG2),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, PAGESZ_LOG2_MIN),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ARF)
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},
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{ XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ENTRIES),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ENTRIES_LOG2),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, PAGESZ_LOG2_MIN),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ARF)
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},
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{ XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ENTRIES),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ENTRIES_LOG2),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, PAGESZ_LOG2_MIN),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ARF)
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},
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{ XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ENTRIES),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ENTRIES_LOG2),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, PAGESZ_LOG2_MIN),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ARF)
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},
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{ XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ENTRIES),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ENTRIES_LOG2),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, PAGESZ_LOG2_MIN),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ARF)
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},
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{ XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ENTRIES),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ENTRIES_LOG2),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, PAGESZ_LOG2_MIN),
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ARF)
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}
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};
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static struct way_config_t dtlb[XCHAL_DTLB_WAYS] =
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{
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{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ENTRIES),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ENTRIES_LOG2),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, PAGESZ_LOG2_MIN),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ARF)
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},
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{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ENTRIES),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ENTRIES_LOG2),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, PAGESZ_LOG2_MIN),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ARF)
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},
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{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ENTRIES),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ENTRIES_LOG2),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, PAGESZ_LOG2_MIN),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ARF)
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},
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{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ENTRIES),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ENTRIES_LOG2),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, PAGESZ_LOG2_MIN),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ARF)
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},
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{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ENTRIES),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ENTRIES_LOG2),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, PAGESZ_LOG2_MIN),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ARF)
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},
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{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ENTRIES),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ENTRIES_LOG2),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, PAGESZ_LOG2_MIN),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ARF)
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},
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{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ENTRIES),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ENTRIES_LOG2),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, PAGESZ_LOG2_MIN),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ARF)
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},
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{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ENTRIES),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ENTRIES_LOG2),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, PAGESZ_LOG2_MIN),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ARF)
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},
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{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ENTRIES),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ENTRIES_LOG2),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, PAGESZ_LOG2_MIN),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ARF)
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},
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{ XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ENTRIES),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ENTRIES_LOG2),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, PAGESZ_LOG2_MIN),
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ARF)
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}
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};
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/* Total number of entries: */
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#define ITLB_TOTAL_ENTRIES \
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ENTRIES) + \
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ENTRIES) + \
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ENTRIES) + \
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ENTRIES) + \
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ENTRIES) + \
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ENTRIES) + \
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XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ENTRIES)
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#define DTLB_TOTAL_ENTRIES \
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ENTRIES) + \
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ENTRIES) + \
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ENTRIES) + \
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ENTRIES) + \
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ENTRIES) + \
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ENTRIES) + \
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ENTRIES) + \
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ENTRIES) + \
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ENTRIES) + \
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XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ENTRIES)
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typedef struct {
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unsigned va;
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unsigned pa;
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unsigned char asid;
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unsigned char ca;
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unsigned char way;
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unsigned char index;
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unsigned char pgsz_log2; /* 0 .. 32 */
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unsigned char type; /* 0=ITLB 1=DTLB */
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} tlb_dump_entry_t;
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/* Return -1 if a precedes b, +1 if a follows b, 0 if same: */
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int cmp_tlb_dump_info( tlb_dump_entry_t *a, tlb_dump_entry_t *b )
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{
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if (a->asid < b->asid) return -1;
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if (a->asid > b->asid) return 1;
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if (a->va < b->va) return -1;
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if (a->va > b->va) return 1;
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if (a->pa < b->pa) return -1;
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if (a->pa > b->pa) return 1;
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if (a->ca < b->ca) return -1;
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if (a->ca > b->ca) return 1;
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if (a->way < b->way) return -1;
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if (a->way > b->way) return 1;
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if (a->index < b->index) return -1;
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if (a->index > b->index) return 1;
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return 0;
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}
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void sort_tlb_dump_info( tlb_dump_entry_t *t, int n )
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{
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int i, j;
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/* Simple O(n*n) sort: */
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for (i = 0; i < n-1; i++)
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for (j = i+1; j < n; j++)
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if (cmp_tlb_dump_info(t+i, t+j) > 0) {
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tlb_dump_entry_t tmp = t[i];
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t[i] = t[j];
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t[j] = tmp;
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}
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}
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static tlb_dump_entry_t itlb_dump_info[ITLB_TOTAL_ENTRIES];
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static tlb_dump_entry_t dtlb_dump_info[DTLB_TOTAL_ENTRIES];
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static inline char *way_type (int type)
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{
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return type ? "autorefill" : "non-autorefill";
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}
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void print_entry (struct way_config_t *way_info,
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unsigned int way,
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unsigned int index,
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unsigned int virtual,
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unsigned int translation)
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{
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char valid_chr;
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unsigned int va, pa, asid, ca;
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va = virtual &
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~((1 << (way_info->pgsz_log2 + way_info->indicies_log2)) - 1);
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asid = virtual & ((1 << XCHAL_MMU_ASID_BITS) - 1);
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pa = translation & ~((1 << way_info->pgsz_log2) - 1);
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ca = translation & ((1 << XCHAL_MMU_CA_BITS) - 1);
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valid_chr = asid ? 'V' : 'I';
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/* Compute and incorporate the effect of the index bits on the
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* va. It's more useful for kernel debugging, since we always
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* want to know the effective va anyway. */
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va += index << way_info->pgsz_log2;
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printk ("\t[%d,%d] (%c) vpn 0x%.8x ppn 0x%.8x asid 0x%.2x am 0x%x\n",
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way, index, valid_chr, va, pa, asid, ca);
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}
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void print_itlb_entry (struct way_config_t *way_info, int way, int index)
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{
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print_entry (way_info, way, index,
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read_itlb_virtual (way + (index << way_info->pgsz_log2)),
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read_itlb_translation (way + (index << way_info->pgsz_log2)));
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}
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void print_dtlb_entry (struct way_config_t *way_info, int way, int index)
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{
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print_entry (way_info, way, index,
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read_dtlb_virtual (way + (index << way_info->pgsz_log2)),
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read_dtlb_translation (way + (index << way_info->pgsz_log2)));
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}
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void dump_itlb (void)
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{
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int way, index;
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printk ("\nITLB: ways = %d\n", XCHAL_ITLB_WAYS);
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for (way = 0; way < XCHAL_ITLB_WAYS; way++) {
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printk ("\nWay: %d, Entries: %d, MinPageSize: %d, Type: %s\n",
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way, itlb[way].indicies,
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itlb[way].pgsz_log2, way_type(itlb[way].arf));
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for (index = 0; index < itlb[way].indicies; index++) {
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print_itlb_entry(&itlb[way], way, index);
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}
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}
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}
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void dump_dtlb (void)
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{
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int way, index;
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printk ("\nDTLB: ways = %d\n", XCHAL_DTLB_WAYS);
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for (way = 0; way < XCHAL_DTLB_WAYS; way++) {
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printk ("\nWay: %d, Entries: %d, MinPageSize: %d, Type: %s\n",
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way, dtlb[way].indicies,
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dtlb[way].pgsz_log2, way_type(dtlb[way].arf));
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for (index = 0; index < dtlb[way].indicies; index++) {
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print_dtlb_entry(&dtlb[way], way, index);
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}
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}
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}
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|
|
|
void dump_tlb (tlb_dump_entry_t *tinfo, struct way_config_t *config,
|
|
int entries, int ways, int type, int show_invalid)
|
|
{
|
|
tlb_dump_entry_t *e = tinfo;
|
|
int way, i;
|
|
|
|
/* Gather all info: */
|
|
for (way = 0; way < ways; way++) {
|
|
struct way_config_t *cfg = config + way;
|
|
for (i = 0; i < cfg->indicies; i++) {
|
|
unsigned wayindex = way + (i << cfg->pgsz_log2);
|
|
unsigned vv = (type ? read_dtlb_virtual (wayindex)
|
|
: read_itlb_virtual (wayindex));
|
|
unsigned pp = (type ? read_dtlb_translation (wayindex)
|
|
: read_itlb_translation (wayindex));
|
|
|
|
/* Compute and incorporate the effect of the index bits on the
|
|
* va. It's more useful for kernel debugging, since we always
|
|
* want to know the effective va anyway. */
|
|
|
|
e->va = (vv & ~((1 << (cfg->pgsz_log2 + cfg->indicies_log2)) - 1));
|
|
e->va += (i << cfg->pgsz_log2);
|
|
e->pa = (pp & ~((1 << cfg->pgsz_log2) - 1));
|
|
e->asid = (vv & ((1 << XCHAL_MMU_ASID_BITS) - 1));
|
|
e->ca = (pp & ((1 << XCHAL_MMU_CA_BITS) - 1));
|
|
e->way = way;
|
|
e->index = i;
|
|
e->pgsz_log2 = cfg->pgsz_log2;
|
|
e->type = type;
|
|
e++;
|
|
}
|
|
}
|
|
#if 1
|
|
/* Sort by ASID and VADDR: */
|
|
sort_tlb_dump_info (tinfo, entries);
|
|
#endif
|
|
|
|
/* Display all sorted info: */
|
|
printk ("\n%cTLB dump:\n", (type ? 'D' : 'I'));
|
|
for (e = tinfo, i = 0; i < entries; i++, e++) {
|
|
#if 0
|
|
if (e->asid == 0 && !show_invalid)
|
|
continue;
|
|
#endif
|
|
printk ("%c way=%d i=%d ASID=%02X V=%08X -> P=%08X CA=%X (%d %cB)\n",
|
|
(e->type ? 'D' : 'I'), e->way, e->index,
|
|
e->asid, e->va, e->pa, e->ca,
|
|
(1 << (e->pgsz_log2 % 10)),
|
|
" kMG"[e->pgsz_log2 / 10]
|
|
);
|
|
}
|
|
}
|
|
|
|
void dump_tlbs2 (int showinv)
|
|
{
|
|
dump_tlb (itlb_dump_info, itlb, ITLB_TOTAL_ENTRIES, XCHAL_ITLB_WAYS, 0, showinv);
|
|
dump_tlb (dtlb_dump_info, dtlb, DTLB_TOTAL_ENTRIES, XCHAL_DTLB_WAYS, 1, showinv);
|
|
}
|
|
|
|
void dump_all_tlbs (void)
|
|
{
|
|
dump_tlbs2 (1);
|
|
}
|
|
|
|
void dump_valid_tlbs (void)
|
|
{
|
|
dump_tlbs2 (0);
|
|
}
|
|
|
|
|
|
void dump_tlbs (void)
|
|
{
|
|
dump_itlb();
|
|
dump_dtlb();
|
|
}
|
|
|
|
void dump_cache_tag(int dcache, int idx)
|
|
{
|
|
int w, i, s, e;
|
|
unsigned long tag, index;
|
|
unsigned long num_lines, num_ways, cache_size, line_size;
|
|
|
|
num_ways = dcache ? XCHAL_DCACHE_WAYS : XCHAL_ICACHE_WAYS;
|
|
cache_size = dcache ? XCHAL_DCACHE_SIZE : XCHAL_ICACHE_SIZE;
|
|
line_size = dcache ? XCHAL_DCACHE_LINESIZE : XCHAL_ICACHE_LINESIZE;
|
|
|
|
num_lines = cache_size / num_ways;
|
|
|
|
s = 0; e = num_lines;
|
|
|
|
if (idx >= 0)
|
|
e = (s = idx * line_size) + 1;
|
|
|
|
for (i = s; i < e; i+= line_size) {
|
|
printk("\nline %#08x:", i);
|
|
for (w = 0; w < num_ways; w++) {
|
|
index = w * num_lines + i;
|
|
if (dcache)
|
|
__asm__ __volatile__("ldct %0, %1\n\t"
|
|
: "=a"(tag) : "a"(index));
|
|
else
|
|
__asm__ __volatile__("lict %0, %1\n\t"
|
|
: "=a"(tag) : "a"(index));
|
|
|
|
printk(" %#010lx", tag);
|
|
}
|
|
}
|
|
printk ("\n");
|
|
}
|
|
|
|
void dump_icache(int index)
|
|
{
|
|
unsigned long data, addr;
|
|
int w, i;
|
|
|
|
const unsigned long num_ways = XCHAL_ICACHE_WAYS;
|
|
const unsigned long cache_size = XCHAL_ICACHE_SIZE;
|
|
const unsigned long line_size = XCHAL_ICACHE_LINESIZE;
|
|
const unsigned long num_lines = cache_size / num_ways / line_size;
|
|
|
|
for (w = 0; w < num_ways; w++) {
|
|
printk ("\nWay %d", w);
|
|
|
|
for (i = 0; i < line_size; i+= 4) {
|
|
addr = w * num_lines + index * line_size + i;
|
|
__asm__ __volatile__("licw %0, %1\n\t"
|
|
: "=a"(data) : "a"(addr));
|
|
printk(" %#010lx", data);
|
|
}
|
|
}
|
|
printk ("\n");
|
|
}
|
|
|
|
void dump_cache_tags(void)
|
|
{
|
|
printk("Instruction cache\n");
|
|
dump_cache_tag(0, -1);
|
|
printk("Data cache\n");
|
|
dump_cache_tag(1, -1);
|
|
}
|
|
|
|
#endif
|