forked from Minki/linux
7d5929c1f3
For v3.12 and prior, 1-bit Hamming code ECC via software was the
default choice. Commit c66d039197 in v3.13 changed the behaviour
to use 1-bit Hamming code via Hardware using a different ECC layout
i.e. (ROM code layout) than what is used by software ECC.
This ECC layout change causes NAND filesystems created in v3.12
and prior to be unusable in v3.13 and later. So revert back to
using software ECC by default if an ECC scheme is not explicitely
specified.
This defect can be observed on the following boards during legacy boot
-omap3beagle
-omap3touchbook
-overo
-am3517crane
-devkit8000
-ldp
-3430sdp
Signed-off-by: Roger Quadros <rogerq@ti.com>
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
246 lines
6.1 KiB
C
246 lines
6.1 KiB
C
/*
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* board-flash.c
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* Modified from mach-omap2/board-3430sdp-flash.c
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*
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* Copyright (C) 2009 Nokia Corporation
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* Copyright (C) 2009 Texas Instruments
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*
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* Vimal Singh <vimalsingh@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/physmap.h>
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#include <linux/io.h>
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#include <linux/platform_data/mtd-nand-omap2.h>
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#include <linux/platform_data/mtd-onenand-omap2.h>
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#include "soc.h"
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#include "common.h"
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#include "board-flash.h"
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#include "gpmc-onenand.h"
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#include "gpmc-nand.h"
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#define REG_FPGA_REV 0x10
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#define REG_FPGA_DIP_SWITCH_INPUT2 0x60
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#define MAX_SUPPORTED_GPMC_CONFIG 3
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#define DEBUG_BASE 0x08000000 /* debug board */
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/* various memory sizes */
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#define FLASH_SIZE_SDPV1 SZ_64M /* NOR flash (64 Meg aligned) */
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#define FLASH_SIZE_SDPV2 SZ_128M /* NOR flash (256 Meg aligned) */
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static struct physmap_flash_data board_nor_data = {
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.width = 2,
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};
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static struct resource board_nor_resource = {
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device board_nor_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &board_nor_data,
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},
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.num_resources = 1,
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.resource = &board_nor_resource,
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};
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static void
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__init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
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{
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int err;
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board_nor_data.parts = nor_parts;
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board_nor_data.nr_parts = nr_parts;
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/* Configure start address and size of NOR device */
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if (omap_rev() >= OMAP3430_REV_ES1_0) {
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err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1,
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(unsigned long *)&board_nor_resource.start);
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board_nor_resource.end = board_nor_resource.start
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+ FLASH_SIZE_SDPV2 - 1;
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} else {
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err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1,
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(unsigned long *)&board_nor_resource.start);
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board_nor_resource.end = board_nor_resource.start
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+ FLASH_SIZE_SDPV1 - 1;
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}
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if (err < 0) {
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pr_err("NOR: Can't request GPMC CS\n");
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return;
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}
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if (platform_device_register(&board_nor_device) < 0)
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pr_err("Unable to register NOR device\n");
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}
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#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
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defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
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static struct omap_onenand_platform_data board_onenand_data = {
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.dma_channel = -1, /* disable DMA in OMAP OneNAND driver */
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};
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void
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__init board_onenand_init(struct mtd_partition *onenand_parts,
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u8 nr_parts, u8 cs)
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{
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board_onenand_data.cs = cs;
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board_onenand_data.parts = onenand_parts;
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board_onenand_data.nr_parts = nr_parts;
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gpmc_onenand_init(&board_onenand_data);
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}
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#endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */
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#if defined(CONFIG_MTD_NAND_OMAP2) || \
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defined(CONFIG_MTD_NAND_OMAP2_MODULE)
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/* Note that all values in this struct are in nanoseconds */
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struct gpmc_timings nand_default_timings[1] = {
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{
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.sync_clk = 0,
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.cs_on = 0,
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.cs_rd_off = 36,
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.cs_wr_off = 36,
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.we_on = 6,
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.oe_on = 6,
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.adv_on = 6,
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.adv_rd_off = 24,
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.adv_wr_off = 36,
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.we_off = 30,
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.oe_off = 48,
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.access = 54,
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.rd_cycle = 72,
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.wr_cycle = 72,
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.wr_access = 30,
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.wr_data_mux_bus = 0,
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},
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};
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static struct omap_nand_platform_data board_nand_data;
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void
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__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
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int nand_type, struct gpmc_timings *gpmc_t)
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{
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board_nand_data.cs = cs;
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board_nand_data.parts = nand_parts;
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board_nand_data.nr_parts = nr_parts;
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board_nand_data.devsize = nand_type;
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board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW;
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gpmc_nand_init(&board_nand_data, gpmc_t);
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}
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#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
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/**
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* get_gpmc0_type - Reads the FPGA DIP_SWITCH_INPUT_REGISTER2 to get
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* the various cs values.
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*/
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static u8 get_gpmc0_type(void)
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{
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u8 cs = 0;
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void __iomem *fpga_map_addr;
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fpga_map_addr = ioremap(DEBUG_BASE, 4096);
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if (!fpga_map_addr)
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return -ENOMEM;
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if (!(readw_relaxed(fpga_map_addr + REG_FPGA_REV)))
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/* we dont have an DEBUG FPGA??? */
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/* Depend on #defines!! default to strata boot return param */
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goto unmap;
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/* S8-DIP-OFF = 1, S8-DIP-ON = 0 */
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cs = readw_relaxed(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
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/* ES2.0 SDP's onwards 4 dip switches are provided for CS */
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if (omap_rev() >= OMAP3430_REV_ES1_0)
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/* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */
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cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) |
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((cs & 2) << 1) | ((cs & 1) << 3);
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else
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/* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */
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cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2);
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unmap:
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iounmap(fpga_map_addr);
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return cs;
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}
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/**
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* board_flash_init - Identify devices connected to GPMC and register.
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*
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* @return - void.
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*/
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void __init board_flash_init(struct flash_partitions partition_info[],
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char chip_sel_board[][GPMC_CS_NUM], int nand_type)
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{
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u8 cs = 0;
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u8 norcs = GPMC_CS_NUM + 1;
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u8 nandcs = GPMC_CS_NUM + 1;
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u8 onenandcs = GPMC_CS_NUM + 1;
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u8 idx;
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unsigned char *config_sel = NULL;
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/* REVISIT: Is this return correct idx for 2430 SDP?
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* for which cs configuration matches for 2430 SDP?
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*/
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idx = get_gpmc0_type();
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if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
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pr_err("%s: Invalid chip select: %d\n", __func__, cs);
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return;
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}
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config_sel = (unsigned char *)(chip_sel_board[idx]);
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while (cs < GPMC_CS_NUM) {
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switch (config_sel[cs]) {
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case PDC_NOR:
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if (norcs > GPMC_CS_NUM)
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norcs = cs;
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break;
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case PDC_NAND:
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if (nandcs > GPMC_CS_NUM)
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nandcs = cs;
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break;
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case PDC_ONENAND:
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if (onenandcs > GPMC_CS_NUM)
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onenandcs = cs;
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break;
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}
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cs++;
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}
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if (norcs > GPMC_CS_NUM)
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pr_err("NOR: Unable to find configuration in GPMC\n");
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else
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board_nor_init(partition_info[0].parts,
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partition_info[0].nr_parts, norcs);
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if (onenandcs > GPMC_CS_NUM)
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pr_err("OneNAND: Unable to find configuration in GPMC\n");
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else
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board_onenand_init(partition_info[1].parts,
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partition_info[1].nr_parts, onenandcs);
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if (nandcs > GPMC_CS_NUM)
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pr_err("NAND: Unable to find configuration in GPMC\n");
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else
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board_nand_init(partition_info[2].parts,
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partition_info[2].nr_parts, nandcs,
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nand_type, nand_default_timings);
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}
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