e37cee133c
The comment about wmb being non-NOP to deal with non-Intel CPUs
is a left over from before the following commit:
09df7c4c80 ("x86: Remove CONFIG_X86_OOSTORE")
It makes no sense now: in particular, wmb() is not a NOP even for
regular Intel CPUs because of weird use-cases e.g. dealing with
WC memory.
Drop this comment.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andrey Konovalov <andreyknvl@google.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Borislav Petkov <bp@suse.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: Davidlohr Bueso <dbueso@suse.de>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: virtualization <virtualization@lists.linux-foundation.org>
Link: http://lkml.kernel.org/r/1453921746-16178-3-git-send-email-mst@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
86 lines
2.1 KiB
C
86 lines
2.1 KiB
C
#ifndef _ASM_X86_BARRIER_H
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#define _ASM_X86_BARRIER_H
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#include <asm/alternative.h>
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#include <asm/nops.h>
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/*
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* Force strict CPU ordering.
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* And yes, this is required on UP too when we're talking
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* to devices.
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*/
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#ifdef CONFIG_X86_32
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#define mb() asm volatile(ALTERNATIVE("lock; addl $0,0(%%esp)", "mfence", \
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X86_FEATURE_XMM2) ::: "memory", "cc")
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#define rmb() asm volatile(ALTERNATIVE("lock; addl $0,0(%%esp)", "lfence", \
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X86_FEATURE_XMM2) ::: "memory", "cc")
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#define wmb() asm volatile(ALTERNATIVE("lock; addl $0,0(%%esp)", "sfence", \
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X86_FEATURE_XMM2) ::: "memory", "cc")
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#else
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#define mb() asm volatile("mfence":::"memory")
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#define rmb() asm volatile("lfence":::"memory")
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#define wmb() asm volatile("sfence" ::: "memory")
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#endif
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#ifdef CONFIG_X86_PPRO_FENCE
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#define dma_rmb() rmb()
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#else
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#define dma_rmb() barrier()
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#endif
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#define dma_wmb() barrier()
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#define __smp_mb() mb()
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#define __smp_rmb() dma_rmb()
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#define __smp_wmb() barrier()
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#define __smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0)
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#if defined(CONFIG_X86_PPRO_FENCE)
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/*
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* For this option x86 doesn't have a strong TSO memory
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* model and we should fall back to full barriers.
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*/
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#define __smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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__smp_mb(); \
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WRITE_ONCE(*p, v); \
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} while (0)
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#define __smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = READ_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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__smp_mb(); \
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___p1; \
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})
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#else /* regular x86 TSO memory ordering */
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#define __smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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WRITE_ONCE(*p, v); \
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} while (0)
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#define __smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = READ_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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___p1; \
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})
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#endif
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/* Atomic operations are already serializing on x86 */
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#define __smp_mb__before_atomic() barrier()
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#define __smp_mb__after_atomic() barrier()
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#include <asm-generic/barrier.h>
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#endif /* _ASM_X86_BARRIER_H */
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