dfed0098ab
HiSilicon accelerators in Hip08 use same hardware scatterlist for data format. We support it in this module. Specific accelerator drivers can use hisi_acc_create_sgl_pool to allocate hardware SGLs ahead. Then use hisi_acc_sg_buf_map_to_hw_sgl to get one hardware SGL and pass related information to hardware SGL. The DMA address of mapped hardware SGL can be passed to SGL src/dst field in QM SQE. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
30 lines
803 B
Plaintext
30 lines
803 B
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config CRYPTO_DEV_HISI_SEC
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tristate "Support for Hisilicon SEC crypto block cipher accelerator"
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select CRYPTO_BLKCIPHER
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select CRYPTO_ALGAPI
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select SG_SPLIT
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depends on ARM64 || COMPILE_TEST
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depends on HAS_IOMEM
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help
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Support for Hisilicon SEC Engine in Hip06 and Hip07
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To compile this as a module, choose M here: the module
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will be called hisi_sec.
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config CRYPTO_DEV_HISI_QM
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tristate
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depends on ARM64 && PCI && PCI_MSI
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help
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HiSilicon accelerator engines use a common queue management
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interface. Specific engine driver may use this module.
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config CRYPTO_HISI_SGL
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tristate
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depends on ARM64
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help
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HiSilicon accelerator engines use a common hardware scatterlist
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interface for data format. Specific engine driver may use this
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module.
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