forked from Minki/linux
dfc25e4503
These cleanup patches are mainly move stuff around and should all
be harmless. They are mainly split out so that other branches can
be based on top to avoid conflicts.
Notable changes are:
* We finally remove all mach/timex.h, after CLOCK_TICK_RATE is no
longer used. (Uwe Kleine-König)
* The Qualcomm MSM platform is split out into legacy mach-msm and
new-style mach-qcom, to allow easier maintainance of the new
hardware support without regressions. (Kumar Gala)
* A rework of some of the Kconfig logic to simplify multiplatform
support (Rob Herring)
* Samsung Exynos gets closer to supporting multiplatform (Sachin
Kamat and others)
* mach-bcm3528 gets merged into mach-bcm (Stephen Warren)
* at91 gains some common clock framework support (Alexandre Belloni,
Jean-Jacques Hiblot and other French people).
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Merge tag 'cleanup-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Arnd Bergmann:
"These cleanup patches are mainly move stuff around and should all be
harmless. They are mainly split out so that other branches can be
based on top to avoid conflicts.
Notable changes are:
- We finally remove all mach/timex.h, after CLOCK_TICK_RATE is no
longer used (Uwe Kleine-König)
- The Qualcomm MSM platform is split out into legacy mach-msm and
new-style mach-qcom, to allow easier maintainance of the new
hardware support without regressions (Kumar Gala)
- A rework of some of the Kconfig logic to simplify multiplatform
support (Rob Herring)
- Samsung Exynos gets closer to supporting multiplatform (Sachin
Kamat and others)
- mach-bcm3528 gets merged into mach-bcm (Stephen Warren)
- at91 gains some common clock framework support (Alexandre Belloni,
Jean-Jacques Hiblot and other French people)"
* tag 'cleanup-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (89 commits)
ARM: hisi: select HAVE_ARM_SCU only for SMP
ARM: efm32: allow uncompress debug output
ARM: prima2: build reset code standalone
ARM: at91: add PWM clock
ARM: at91: move sam9261 SoC to common clk
ARM: at91: prepare common clk transition for sam9261 SoC
ARM: at91: updated the at91_dt_defconfig with support for the ADS7846
ARM: at91: dt: sam9261: Device Tree support for the at91sam9261ek
ARM: at91: dt: defconfig: Added the sam9261 to the list of DT-enabled SOCs
ARM: at91: dt: Add at91sam9261 dt SoC support
ARM: at91: switch sam9rl to common clock framework
ARM: at91/dt: define main clk frequency of at91sam9rlek
ARM: at91/dt: define at91sam9rl clocks
ARM: at91: prepare common clk transition for sam9rl SoCs
ARM: at91: prepare sam9 dt boards transition to common clk
ARM: at91: dt: sam9rl: Device Tree for the at91sam9rlek
ARM: at91/defconfig: Add the sam9rl to the list of DT-enabled SOCs
ARM: at91: Add at91sam9rl DT SoC support
ARM: at91: prepare at91sam9rl DT transition
ARM: at91/defconfig: refresh at91sam9260_9g20_defconfig
...
764 lines
22 KiB
Plaintext
764 lines
22 KiB
Plaintext
/*
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* DTS file for CSR SiRFatlas6 SoC
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*
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* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "sirf,atlas6";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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reg = <0x0>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <32768>;
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i-cache-size = <32768>;
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/* from bootloader */
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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clocks = <&clks 12>;
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operating-points = <
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/* kHz uV */
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200000 1025000
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400000 1025000
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600000 1050000
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800000 1100000
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>;
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clock-latency = <150000>;
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};
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};
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axi {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x40000000 0x40000000 0x80000000>;
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intc: interrupt-controller@80020000 {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "sirf,prima2-intc";
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reg = <0x80020000 0x1000>;
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};
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sys-iobg {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x88000000 0x88000000 0x40000>;
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clks: clock-controller@88000000 {
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compatible = "sirf,atlas6-clkc";
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reg = <0x88000000 0x1000>;
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interrupts = <3>;
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#clock-cells = <1>;
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};
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rstc: reset-controller@88010000 {
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compatible = "sirf,prima2-rstc";
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reg = <0x88010000 0x1000>;
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#reset-cells = <1>;
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};
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rsc-controller@88020000 {
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compatible = "sirf,prima2-rsc";
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reg = <0x88020000 0x1000>;
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};
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cphifbg@88030000 {
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compatible = "sirf,prima2-cphifbg";
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reg = <0x88030000 0x1000>;
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clocks = <&clks 42>;
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};
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};
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mem-iobg {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x90000000 0x90000000 0x10000>;
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memory-controller@90000000 {
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compatible = "sirf,prima2-memc";
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reg = <0x90000000 0x2000>;
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interrupts = <27>;
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clocks = <&clks 5>;
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};
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memc-monitor {
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compatible = "sirf,prima2-memcmon";
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reg = <0x90002000 0x200>;
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interrupts = <4>;
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clocks = <&clks 32>;
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};
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};
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disp-iobg {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x90010000 0x90010000 0x30000>;
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lcd@90010000 {
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compatible = "sirf,prima2-lcd";
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reg = <0x90010000 0x20000>;
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interrupts = <30>;
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clocks = <&clks 34>;
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display=<&display>;
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/* later transfer to pwm */
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bl-gpio = <&gpio 7 0>;
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default-panel = <&panel0>;
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};
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vpp@90020000 {
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compatible = "sirf,prima2-vpp";
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reg = <0x90020000 0x10000>;
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interrupts = <31>;
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clocks = <&clks 35>;
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};
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};
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graphics-iobg {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x98000000 0x98000000 0x8000000>;
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graphics@98000000 {
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compatible = "powervr,sgx510";
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reg = <0x98000000 0x8000000>;
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interrupts = <6>;
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clocks = <&clks 32>;
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};
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};
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graphics2d-iobg {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xa0000000 0xa0000000 0x8000000>;
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ble@a0000000 {
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compatible = "sirf,atlas6-ble";
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reg = <0xa0000000 0x2000>;
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interrupts = <5>;
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clocks = <&clks 33>;
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};
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};
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dsp-iobg {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xa8000000 0xa8000000 0x2000000>;
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dspif@a8000000 {
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compatible = "sirf,prima2-dspif";
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reg = <0xa8000000 0x10000>;
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interrupts = <9>;
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};
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gps@a8010000 {
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compatible = "sirf,prima2-gps";
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reg = <0xa8010000 0x10000>;
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interrupts = <7>;
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clocks = <&clks 9>;
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};
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dsp@a9000000 {
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compatible = "sirf,prima2-dsp";
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reg = <0xa9000000 0x1000000>;
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interrupts = <8>;
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clocks = <&clks 8>;
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};
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};
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peri-iobg {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xb0000000 0xb0000000 0x180000>,
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<0x56000000 0x56000000 0x1b00000>;
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timer@b0020000 {
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compatible = "sirf,prima2-tick";
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reg = <0xb0020000 0x1000>;
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interrupts = <0>;
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};
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nand@b0030000 {
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compatible = "sirf,prima2-nand";
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reg = <0xb0030000 0x10000>;
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interrupts = <41>;
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clocks = <&clks 26>;
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};
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audio@b0040000 {
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compatible = "sirf,prima2-audio";
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reg = <0xb0040000 0x10000>;
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interrupts = <35>;
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clocks = <&clks 27>;
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};
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uart0: uart@b0050000 {
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cell-index = <0>;
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compatible = "sirf,prima2-uart";
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reg = <0xb0050000 0x1000>;
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interrupts = <17>;
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fifosize = <128>;
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clocks = <&clks 13>;
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dmas = <&dmac1 5>, <&dmac0 2>;
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dma-names = "rx", "tx";
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};
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uart1: uart@b0060000 {
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cell-index = <1>;
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compatible = "sirf,prima2-uart";
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reg = <0xb0060000 0x1000>;
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interrupts = <18>;
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fifosize = <32>;
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clocks = <&clks 14>;
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dma-names = "no-rx", "no-tx";
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};
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uart2: uart@b0070000 {
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cell-index = <2>;
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compatible = "sirf,prima2-uart";
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reg = <0xb0070000 0x1000>;
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interrupts = <19>;
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fifosize = <128>;
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clocks = <&clks 15>;
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dmas = <&dmac0 6>, <&dmac0 7>;
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dma-names = "rx", "tx";
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};
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usp0: usp@b0080000 {
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cell-index = <0>;
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compatible = "sirf,prima2-usp";
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reg = <0xb0080000 0x10000>;
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interrupts = <20>;
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fifosize = <128>;
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clocks = <&clks 28>;
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dmas = <&dmac1 1>, <&dmac1 2>;
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dma-names = "rx", "tx";
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};
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usp1: usp@b0090000 {
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cell-index = <1>;
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compatible = "sirf,prima2-usp";
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reg = <0xb0090000 0x10000>;
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interrupts = <21>;
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fifosize = <128>;
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clocks = <&clks 29>;
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dmas = <&dmac0 14>, <&dmac0 15>;
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dma-names = "rx", "tx";
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};
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dmac0: dma-controller@b00b0000 {
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cell-index = <0>;
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compatible = "sirf,prima2-dmac";
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reg = <0xb00b0000 0x10000>;
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interrupts = <12>;
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clocks = <&clks 24>;
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};
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dmac1: dma-controller@b0160000 {
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cell-index = <1>;
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compatible = "sirf,prima2-dmac";
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reg = <0xb0160000 0x10000>;
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interrupts = <13>;
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clocks = <&clks 25>;
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};
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vip@b00C0000 {
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compatible = "sirf,prima2-vip";
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reg = <0xb00C0000 0x10000>;
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clocks = <&clks 31>;
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interrupts = <14>;
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sirf,vip-dma-rx-channel = <16>;
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};
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spi0: spi@b00d0000 {
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cell-index = <0>;
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compatible = "sirf,prima2-spi";
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reg = <0xb00d0000 0x10000>;
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interrupts = <15>;
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sirf,spi-num-chipselects = <1>;
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cs-gpios = <&gpio 0 0>;
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sirf,spi-dma-rx-channel = <25>;
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sirf,spi-dma-tx-channel = <20>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clks 19>;
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status = "disabled";
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};
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spi1: spi@b0170000 {
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cell-index = <1>;
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compatible = "sirf,prima2-spi";
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reg = <0xb0170000 0x10000>;
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interrupts = <16>;
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sirf,spi-num-chipselects = <1>;
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sirf,spi-dma-rx-channel = <12>;
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sirf,spi-dma-tx-channel = <13>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clks 20>;
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status = "disabled";
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};
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i2c0: i2c@b00e0000 {
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cell-index = <0>;
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compatible = "sirf,prima2-i2c";
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reg = <0xb00e0000 0x10000>;
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interrupts = <24>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clks 17>;
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};
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i2c1: i2c@b00f0000 {
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cell-index = <1>;
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compatible = "sirf,prima2-i2c";
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reg = <0xb00f0000 0x10000>;
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|
interrupts = <25>;
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|
#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clks 18>;
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};
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|
tsc@b0110000 {
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compatible = "sirf,prima2-tsc";
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reg = <0xb0110000 0x10000>;
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|
interrupts = <33>;
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|
clocks = <&clks 16>;
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};
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gpio: pinctrl@b0120000 {
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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compatible = "sirf,atlas6-pinctrl";
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reg = <0xb0120000 0x10000>;
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interrupts = <43 44 45 46 47>;
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gpio-controller;
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interrupt-controller;
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lcd_16pins_a: lcd0@0 {
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lcd {
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sirf,pins = "lcd_16bitsgrp";
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sirf,function = "lcd_16bits";
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};
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};
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lcd_18pins_a: lcd0@1 {
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lcd {
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sirf,pins = "lcd_18bitsgrp";
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sirf,function = "lcd_18bits";
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};
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};
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lcd_24pins_a: lcd0@2 {
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lcd {
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sirf,pins = "lcd_24bitsgrp";
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sirf,function = "lcd_24bits";
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};
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};
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lcdrom_pins_a: lcdrom0@0 {
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lcd {
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sirf,pins = "lcdromgrp";
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sirf,function = "lcdrom";
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};
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};
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uart0_pins_a: uart0@0 {
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uart {
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sirf,pins = "uart0grp";
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sirf,function = "uart0";
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};
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};
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uart0_noflow_pins_a: uart0@1 {
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uart {
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sirf,pins = "uart0_nostreamctrlgrp";
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sirf,function = "uart0_nostreamctrl";
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};
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};
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uart1_pins_a: uart1@0 {
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uart {
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sirf,pins = "uart1grp";
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sirf,function = "uart1";
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};
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};
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uart2_pins_a: uart2@0 {
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uart {
|
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sirf,pins = "uart2grp";
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sirf,function = "uart2";
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};
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};
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uart2_noflow_pins_a: uart2@1 {
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uart {
|
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sirf,pins = "uart2_nostreamctrlgrp";
|
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sirf,function = "uart2_nostreamctrl";
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};
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};
|
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spi0_pins_a: spi0@0 {
|
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spi {
|
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sirf,pins = "spi0grp";
|
|
sirf,function = "spi0";
|
|
};
|
|
};
|
|
spi1_pins_a: spi1@0 {
|
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spi {
|
|
sirf,pins = "spi1grp";
|
|
sirf,function = "spi1";
|
|
};
|
|
};
|
|
i2c0_pins_a: i2c0@0 {
|
|
i2c {
|
|
sirf,pins = "i2c0grp";
|
|
sirf,function = "i2c0";
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|
};
|
|
};
|
|
i2c1_pins_a: i2c1@0 {
|
|
i2c {
|
|
sirf,pins = "i2c1grp";
|
|
sirf,function = "i2c1";
|
|
};
|
|
};
|
|
pwm0_pins_a: pwm0@0 {
|
|
pwm {
|
|
sirf,pins = "pwm0grp";
|
|
sirf,function = "pwm0";
|
|
};
|
|
};
|
|
pwm1_pins_a: pwm1@0 {
|
|
pwm {
|
|
sirf,pins = "pwm1grp";
|
|
sirf,function = "pwm1";
|
|
};
|
|
};
|
|
pwm2_pins_a: pwm2@0 {
|
|
pwm {
|
|
sirf,pins = "pwm2grp";
|
|
sirf,function = "pwm2";
|
|
};
|
|
};
|
|
pwm3_pins_a: pwm3@0 {
|
|
pwm {
|
|
sirf,pins = "pwm3grp";
|
|
sirf,function = "pwm3";
|
|
};
|
|
};
|
|
pwm4_pins_a: pwm4@0 {
|
|
pwm {
|
|
sirf,pins = "pwm4grp";
|
|
sirf,function = "pwm4";
|
|
};
|
|
};
|
|
gps_pins_a: gps@0 {
|
|
gps {
|
|
sirf,pins = "gpsgrp";
|
|
sirf,function = "gps";
|
|
};
|
|
};
|
|
vip_pins_a: vip@0 {
|
|
vip {
|
|
sirf,pins = "vipgrp";
|
|
sirf,function = "vip";
|
|
};
|
|
};
|
|
sdmmc0_pins_a: sdmmc0@0 {
|
|
sdmmc0 {
|
|
sirf,pins = "sdmmc0grp";
|
|
sirf,function = "sdmmc0";
|
|
};
|
|
};
|
|
sdmmc1_pins_a: sdmmc1@0 {
|
|
sdmmc1 {
|
|
sirf,pins = "sdmmc1grp";
|
|
sirf,function = "sdmmc1";
|
|
};
|
|
};
|
|
sdmmc2_pins_a: sdmmc2@0 {
|
|
sdmmc2 {
|
|
sirf,pins = "sdmmc2grp";
|
|
sirf,function = "sdmmc2";
|
|
};
|
|
};
|
|
sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
|
|
sdmmc2_nowp {
|
|
sirf,pins = "sdmmc2_nowpgrp";
|
|
sirf,function = "sdmmc2_nowp";
|
|
};
|
|
};
|
|
sdmmc3_pins_a: sdmmc3@0 {
|
|
sdmmc3 {
|
|
sirf,pins = "sdmmc3grp";
|
|
sirf,function = "sdmmc3";
|
|
};
|
|
};
|
|
sdmmc5_pins_a: sdmmc5@0 {
|
|
sdmmc5 {
|
|
sirf,pins = "sdmmc5grp";
|
|
sirf,function = "sdmmc5";
|
|
};
|
|
};
|
|
i2s_pins_a: i2s@0 {
|
|
i2s {
|
|
sirf,pins = "i2sgrp";
|
|
sirf,function = "i2s";
|
|
};
|
|
};
|
|
i2s_no_din_pins_a: i2s_no_din@0 {
|
|
i2s_no_din {
|
|
sirf,pins = "i2s_no_dingrp";
|
|
sirf,function = "i2s_no_din";
|
|
};
|
|
};
|
|
i2s_6chn_pins_a: i2s_6chn@0 {
|
|
i2s_6chn {
|
|
sirf,pins = "i2s_6chngrp";
|
|
sirf,function = "i2s_6chn";
|
|
};
|
|
};
|
|
ac97_pins_a: ac97@0 {
|
|
ac97 {
|
|
sirf,pins = "ac97grp";
|
|
sirf,function = "ac97";
|
|
};
|
|
};
|
|
nand_pins_a: nand@0 {
|
|
nand {
|
|
sirf,pins = "nandgrp";
|
|
sirf,function = "nand";
|
|
};
|
|
};
|
|
usp0_pins_a: usp0@0 {
|
|
usp0 {
|
|
sirf,pins = "usp0grp";
|
|
sirf,function = "usp0";
|
|
};
|
|
};
|
|
usp0_uart_nostreamctrl_pins_a: usp0@1 {
|
|
usp0 {
|
|
sirf,pins = "usp0_uart_nostreamctrl_grp";
|
|
sirf,function = "usp0_uart_nostreamctrl";
|
|
};
|
|
};
|
|
usp1_pins_a: usp1@0 {
|
|
usp1 {
|
|
sirf,pins = "usp1grp";
|
|
sirf,function = "usp1";
|
|
};
|
|
};
|
|
usp1_uart_nostreamctrl_pins_a: usp1@1 {
|
|
usp1 {
|
|
sirf,pins = "usp1_uart_nostreamctrl_grp";
|
|
sirf,function = "usp1_uart_nostreamctrl";
|
|
};
|
|
};
|
|
usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
|
|
usb0_upli_drvbus {
|
|
sirf,pins = "usb0_upli_drvbusgrp";
|
|
sirf,function = "usb0_upli_drvbus";
|
|
};
|
|
};
|
|
usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
|
|
usb1_utmi_drvbus {
|
|
sirf,pins = "usb1_utmi_drvbusgrp";
|
|
sirf,function = "usb1_utmi_drvbus";
|
|
};
|
|
};
|
|
usb1_dp_dn_pins_a: usb1_dp_dn@0 {
|
|
usb1_dp_dn {
|
|
sirf,pins = "usb1_dp_dngrp";
|
|
sirf,function = "usb1_dp_dn";
|
|
};
|
|
};
|
|
uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
|
|
uart1_route_io_usb1 {
|
|
sirf,pins = "uart1_route_io_usb1grp";
|
|
sirf,function = "uart1_route_io_usb1";
|
|
};
|
|
};
|
|
warm_rst_pins_a: warm_rst@0 {
|
|
warm_rst {
|
|
sirf,pins = "warm_rstgrp";
|
|
sirf,function = "warm_rst";
|
|
};
|
|
};
|
|
pulse_count_pins_a: pulse_count@0 {
|
|
pulse_count {
|
|
sirf,pins = "pulse_countgrp";
|
|
sirf,function = "pulse_count";
|
|
};
|
|
};
|
|
cko0_pins_a: cko0@0 {
|
|
cko0 {
|
|
sirf,pins = "cko0grp";
|
|
sirf,function = "cko0";
|
|
};
|
|
};
|
|
cko1_pins_a: cko1@0 {
|
|
cko1 {
|
|
sirf,pins = "cko1grp";
|
|
sirf,function = "cko1";
|
|
};
|
|
};
|
|
};
|
|
|
|
pwm@b0130000 {
|
|
compatible = "sirf,prima2-pwm";
|
|
reg = <0xb0130000 0x10000>;
|
|
clocks = <&clks 21>;
|
|
};
|
|
|
|
efusesys@b0140000 {
|
|
compatible = "sirf,prima2-efuse";
|
|
reg = <0xb0140000 0x10000>;
|
|
clocks = <&clks 22>;
|
|
};
|
|
|
|
pulsec@b0150000 {
|
|
compatible = "sirf,prima2-pulsec";
|
|
reg = <0xb0150000 0x10000>;
|
|
interrupts = <48>;
|
|
clocks = <&clks 23>;
|
|
};
|
|
|
|
pci-iobg {
|
|
compatible = "sirf,prima2-pciiobg", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x56000000 0x56000000 0x1b00000>;
|
|
|
|
sd0: sdhci@56000000 {
|
|
cell-index = <0>;
|
|
compatible = "sirf,prima2-sdhc";
|
|
reg = <0x56000000 0x100000>;
|
|
interrupts = <38>;
|
|
bus-width = <8>;
|
|
clocks = <&clks 36>;
|
|
};
|
|
|
|
sd1: sdhci@56100000 {
|
|
cell-index = <1>;
|
|
compatible = "sirf,prima2-sdhc";
|
|
reg = <0x56100000 0x100000>;
|
|
interrupts = <38>;
|
|
status = "disabled";
|
|
bus-width = <4>;
|
|
clocks = <&clks 36>;
|
|
};
|
|
|
|
sd2: sdhci@56200000 {
|
|
cell-index = <2>;
|
|
compatible = "sirf,prima2-sdhc";
|
|
reg = <0x56200000 0x100000>;
|
|
interrupts = <23>;
|
|
status = "disabled";
|
|
bus-width = <4>;
|
|
clocks = <&clks 37>;
|
|
};
|
|
|
|
sd3: sdhci@56300000 {
|
|
cell-index = <3>;
|
|
compatible = "sirf,prima2-sdhc";
|
|
reg = <0x56300000 0x100000>;
|
|
interrupts = <23>;
|
|
status = "disabled";
|
|
bus-width = <4>;
|
|
clocks = <&clks 37>;
|
|
};
|
|
|
|
sd5: sdhci@56500000 {
|
|
cell-index = <5>;
|
|
compatible = "sirf,prima2-sdhc";
|
|
reg = <0x56500000 0x100000>;
|
|
interrupts = <39>;
|
|
status = "disabled";
|
|
bus-width = <4>;
|
|
clocks = <&clks 38>;
|
|
};
|
|
|
|
pci-copy@57900000 {
|
|
compatible = "sirf,prima2-pcicp";
|
|
reg = <0x57900000 0x100000>;
|
|
interrupts = <40>;
|
|
};
|
|
|
|
rom-interface@57a00000 {
|
|
compatible = "sirf,prima2-romif";
|
|
reg = <0x57a00000 0x100000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
rtc-iobg {
|
|
compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x80030000 0x10000>;
|
|
|
|
gpsrtc@1000 {
|
|
compatible = "sirf,prima2-gpsrtc";
|
|
reg = <0x1000 0x1000>;
|
|
interrupts = <55 56 57>;
|
|
};
|
|
|
|
sysrtc@2000 {
|
|
compatible = "sirf,prima2-sysrtc";
|
|
reg = <0x2000 0x1000>;
|
|
interrupts = <52 53 54>;
|
|
};
|
|
|
|
minigpsrtc@2000 {
|
|
compatible = "sirf,prima2-minigpsrtc";
|
|
reg = <0x2000 0x1000>;
|
|
interrupts = <54>;
|
|
};
|
|
|
|
pwrc@3000 {
|
|
compatible = "sirf,prima2-pwrc";
|
|
reg = <0x3000 0x1000>;
|
|
interrupts = <32>;
|
|
};
|
|
};
|
|
|
|
uus-iobg {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0xb8000000 0xb8000000 0x40000>;
|
|
|
|
usb0: usb@b00e0000 {
|
|
compatible = "chipidea,ci13611a-prima2";
|
|
reg = <0xb8000000 0x10000>;
|
|
interrupts = <10>;
|
|
clocks = <&clks 40>;
|
|
};
|
|
|
|
usb1: usb@b00f0000 {
|
|
compatible = "chipidea,ci13611a-prima2";
|
|
reg = <0xb8010000 0x10000>;
|
|
interrupts = <11>;
|
|
clocks = <&clks 41>;
|
|
};
|
|
|
|
security@b00f0000 {
|
|
compatible = "sirf,prima2-security";
|
|
reg = <0xb8030000 0x10000>;
|
|
interrupts = <42>;
|
|
clocks = <&clks 7>;
|
|
};
|
|
};
|
|
};
|
|
};
|