11b897cf84
On Alchemy the PCMCIA area lies at the end of the chips 36bit system bus area. Currently, addresses at the far end of the 32bit area are assumed to belong to the PCMCIA area and fixed up to the real 36bit address before being passed to ioremap(). A previous commit enabled 64 bit physical size for the resource datatype on Alchemy and this allows to use the correct 36bit addresses when registering the PCMCIA sockets. This patch removes the 32-to-36bit address fixup and registers the Alchemy demo board pcmcia socket with the correct 36bit physical addresses. Tested on DB1200, with a CF card (ide-cs driver) and a 3c589 PCMCIA ethernet card. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: Manuel Lauss <manuel.lauss@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/994/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
119 lines
4.0 KiB
C
119 lines
4.0 KiB
C
/*
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* DBAu1xxx board platform device registration
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*
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* Copyright (C) 2009 Manuel Lauss
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <asm/mach-au1x00/au1xxx.h>
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#include <asm/mach-db1x00/bcsr.h>
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#include "../platform.h"
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/* DB1xxx PCMCIA interrupt sources:
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* CD0/1 GPIO0/3
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* STSCHG0/1 GPIO1/4
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* CARD0/1 GPIO2/5
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* Db1550: 0/1, 21/22, 3/5
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*/
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#define DB1XXX_HAS_PCMCIA
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#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
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#if defined(CONFIG_MIPS_DB1000)
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#define DB1XXX_PCMCIA_CD0 AU1000_GPIO0_INT
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#define DB1XXX_PCMCIA_STSCHG0 AU1000_GPIO1_INT
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#define DB1XXX_PCMCIA_CARD0 AU1000_GPIO2_INT
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#define DB1XXX_PCMCIA_CD1 AU1000_GPIO3_INT
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#define DB1XXX_PCMCIA_STSCHG1 AU1000_GPIO4_INT
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#define DB1XXX_PCMCIA_CARD1 AU1000_GPIO5_INT
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#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
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#define BOARD_FLASH_WIDTH 4 /* 32-bits */
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#elif defined(CONFIG_MIPS_DB1100)
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#define DB1XXX_PCMCIA_CD0 AU1100_GPIO0_INT
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#define DB1XXX_PCMCIA_STSCHG0 AU1100_GPIO1_INT
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#define DB1XXX_PCMCIA_CARD0 AU1100_GPIO2_INT
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#define DB1XXX_PCMCIA_CD1 AU1100_GPIO3_INT
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#define DB1XXX_PCMCIA_STSCHG1 AU1100_GPIO4_INT
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#define DB1XXX_PCMCIA_CARD1 AU1100_GPIO5_INT
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#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
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#define BOARD_FLASH_WIDTH 4 /* 32-bits */
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#elif defined(CONFIG_MIPS_DB1500)
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#define DB1XXX_PCMCIA_CD0 AU1500_GPIO0_INT
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#define DB1XXX_PCMCIA_STSCHG0 AU1500_GPIO1_INT
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#define DB1XXX_PCMCIA_CARD0 AU1500_GPIO2_INT
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#define DB1XXX_PCMCIA_CD1 AU1500_GPIO3_INT
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#define DB1XXX_PCMCIA_STSCHG1 AU1500_GPIO4_INT
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#define DB1XXX_PCMCIA_CARD1 AU1500_GPIO5_INT
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#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
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#define BOARD_FLASH_WIDTH 4 /* 32-bits */
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#elif defined(CONFIG_MIPS_DB1550)
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#define DB1XXX_PCMCIA_CD0 AU1550_GPIO0_INT
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#define DB1XXX_PCMCIA_STSCHG0 AU1550_GPIO21_INT
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#define DB1XXX_PCMCIA_CARD0 AU1550_GPIO3_INT
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#define DB1XXX_PCMCIA_CD1 AU1550_GPIO1_INT
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#define DB1XXX_PCMCIA_STSCHG1 AU1550_GPIO22_INT
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#define DB1XXX_PCMCIA_CARD1 AU1550_GPIO5_INT
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#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */
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#define BOARD_FLASH_WIDTH 4 /* 32-bits */
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#else
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/* other board: no PCMCIA */
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#undef DB1XXX_HAS_PCMCIA
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#undef F_SWAPPED
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#define F_SWAPPED 0
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#if defined(CONFIG_MIPS_BOSPORUS)
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#define BOARD_FLASH_SIZE 0x01000000 /* 16MB */
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#define BOARD_FLASH_WIDTH 2 /* 16-bits */
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#elif defined(CONFIG_MIPS_MIRAGE)
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#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
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#define BOARD_FLASH_WIDTH 4 /* 32-bits */
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#endif
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#endif
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static int __init db1xxx_dev_init(void)
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{
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#ifdef DB1XXX_HAS_PCMCIA
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db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
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PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
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PCMCIA_MEM_PHYS_ADDR,
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PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
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PCMCIA_IO_PHYS_ADDR,
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PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
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DB1XXX_PCMCIA_CARD0,
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DB1XXX_PCMCIA_CD0,
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/*DB1XXX_PCMCIA_STSCHG0*/0,
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0,
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0);
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db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
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PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
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PCMCIA_MEM_PHYS_ADDR + 0x004000000,
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PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
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PCMCIA_IO_PHYS_ADDR + 0x004000000,
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PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
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DB1XXX_PCMCIA_CARD1,
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DB1XXX_PCMCIA_CD1,
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/*DB1XXX_PCMCIA_STSCHG1*/0,
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0,
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1);
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#endif
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db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED);
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return 0;
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}
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device_initcall(db1xxx_dev_init);
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