Tony Cheng d98e5cc2dd drm/amd/display: clean up and simply locking logic ... always take update lock instead of using HW built in update lock trigger with write to primary_addr_lo. we will be a little more inefficient with the extra registers write to lock, but this simplify code and make it always correct. Will revisit locking optimization once update sequence mature Signed-off-by: Tony Cheng <tony.cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2017-09-26 17:17:51 -04:00
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hw	drm/amd/display: add scaler coefficients for 64 phase 5-8 taps	2017-09-26 17:16:09 -04:00
bandwidth_calcs.h	drm/amd/display: Support 64-bit Polaris11 5k VSR	2017-09-26 17:09:20 -04:00
bw_fixed.h
clock_source.h	drm/amd/display: HDMI YCbCr422 12bpc pixel format issue	2017-09-26 17:13:37 -04:00
compressor.h
core_dc.h	drm/amd/display: Remove dc_target object	2017-09-26 17:09:40 -04:00
core_status.h	drm/amd/display: remove apply_clk_constraints, used validate_bandwidth universally	2017-09-26 17:16:27 -04:00
core_types.h	drm/amd/display: remove apply_clk_constraints, used validate_bandwidth universally	2017-09-26 17:16:27 -04:00
custom_float.h	drm/amd/display: Enable regamma 25 segments and use double buffer.	2017-09-26 17:14:18 -04:00
dc_link_ddc.h
dc_link_dp.h
hw_sequencer.h	drm/amd/display: clean up and simply locking logic	2017-09-26 17:17:51 -04:00
link_hwss.h	drm/amd/display: Fix link retraining hw sequence for auto test	2017-09-26 17:08:10 -04:00
reg_helper.h	drm/amd/display: define reg helpers to update registers with 8 and 9 fields	2017-09-26 17:05:36 -04:00
resource.h	drm/amd/display: Remove dc_target object	2017-09-26 17:09:40 -04:00