forked from Minki/linux
e654df7a1a
The CG8 field of the CCM CCGR3 register is the 'mipi_core_cfg' gate clock, according to the i.MX6q/sdl reference manuals. This clock is actually the gate for several clocks, including the ipg clock's output. The MIPI DSI host controller embedded in the i.MX6q/sdl SoCs takes the ipg clock as the pclk - the APB clock signal . In order to gate/ungate the ipg clock, this patch adds a new shared clock gate named as "mipi_ipg". Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
257 lines
8.7 KiB
C
257 lines
8.7 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
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#define __DT_BINDINGS_CLOCK_IMX6QDL_H
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#define IMX6QDL_CLK_DUMMY 0
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#define IMX6QDL_CLK_CKIL 1
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#define IMX6QDL_CLK_CKIH 2
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#define IMX6QDL_CLK_OSC 3
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#define IMX6QDL_CLK_PLL2_PFD0_352M 4
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#define IMX6QDL_CLK_PLL2_PFD1_594M 5
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#define IMX6QDL_CLK_PLL2_PFD2_396M 6
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#define IMX6QDL_CLK_PLL3_PFD0_720M 7
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#define IMX6QDL_CLK_PLL3_PFD1_540M 8
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#define IMX6QDL_CLK_PLL3_PFD2_508M 9
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#define IMX6QDL_CLK_PLL3_PFD3_454M 10
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#define IMX6QDL_CLK_PLL2_198M 11
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#define IMX6QDL_CLK_PLL3_120M 12
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#define IMX6QDL_CLK_PLL3_80M 13
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#define IMX6QDL_CLK_PLL3_60M 14
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#define IMX6QDL_CLK_TWD 15
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#define IMX6QDL_CLK_STEP 16
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#define IMX6QDL_CLK_PLL1_SW 17
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#define IMX6QDL_CLK_PERIPH_PRE 18
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#define IMX6QDL_CLK_PERIPH2_PRE 19
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#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20
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#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21
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#define IMX6QDL_CLK_AXI_SEL 22
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#define IMX6QDL_CLK_ESAI_SEL 23
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#define IMX6QDL_CLK_ASRC_SEL 24
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#define IMX6QDL_CLK_SPDIF_SEL 25
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#define IMX6QDL_CLK_GPU2D_AXI 26
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#define IMX6QDL_CLK_GPU3D_AXI 27
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#define IMX6QDL_CLK_GPU2D_CORE_SEL 28
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#define IMX6QDL_CLK_GPU3D_CORE_SEL 29
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#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30
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#define IMX6QDL_CLK_IPU1_SEL 31
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#define IMX6QDL_CLK_IPU2_SEL 32
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#define IMX6QDL_CLK_LDB_DI0_SEL 33
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#define IMX6QDL_CLK_LDB_DI1_SEL 34
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#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35
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#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36
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#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37
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#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38
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#define IMX6QDL_CLK_IPU1_DI0_SEL 39
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#define IMX6QDL_CLK_IPU1_DI1_SEL 40
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#define IMX6QDL_CLK_IPU2_DI0_SEL 41
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#define IMX6QDL_CLK_IPU2_DI1_SEL 42
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#define IMX6QDL_CLK_HSI_TX_SEL 43
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#define IMX6QDL_CLK_PCIE_AXI_SEL 44
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#define IMX6QDL_CLK_SSI1_SEL 45
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#define IMX6QDL_CLK_SSI2_SEL 46
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#define IMX6QDL_CLK_SSI3_SEL 47
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#define IMX6QDL_CLK_USDHC1_SEL 48
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#define IMX6QDL_CLK_USDHC2_SEL 49
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#define IMX6QDL_CLK_USDHC3_SEL 50
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#define IMX6QDL_CLK_USDHC4_SEL 51
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#define IMX6QDL_CLK_ENFC_SEL 52
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#define IMX6QDL_CLK_EIM_SEL 53
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#define IMX6QDL_CLK_EIM_SLOW_SEL 54
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#define IMX6QDL_CLK_VDO_AXI_SEL 55
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#define IMX6QDL_CLK_VPU_AXI_SEL 56
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#define IMX6QDL_CLK_CKO1_SEL 57
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#define IMX6QDL_CLK_PERIPH 58
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#define IMX6QDL_CLK_PERIPH2 59
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#define IMX6QDL_CLK_PERIPH_CLK2 60
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#define IMX6QDL_CLK_PERIPH2_CLK2 61
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#define IMX6QDL_CLK_IPG 62
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#define IMX6QDL_CLK_IPG_PER 63
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#define IMX6QDL_CLK_ESAI_PRED 64
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#define IMX6QDL_CLK_ESAI_PODF 65
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#define IMX6QDL_CLK_ASRC_PRED 66
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#define IMX6QDL_CLK_ASRC_PODF 67
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#define IMX6QDL_CLK_SPDIF_PRED 68
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#define IMX6QDL_CLK_SPDIF_PODF 69
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#define IMX6QDL_CLK_CAN_ROOT 70
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#define IMX6QDL_CLK_ECSPI_ROOT 71
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#define IMX6QDL_CLK_GPU2D_CORE_PODF 72
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#define IMX6QDL_CLK_GPU3D_CORE_PODF 73
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#define IMX6QDL_CLK_GPU3D_SHADER 74
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#define IMX6QDL_CLK_IPU1_PODF 75
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#define IMX6QDL_CLK_IPU2_PODF 76
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#define IMX6QDL_CLK_LDB_DI0_PODF 77
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#define IMX6QDL_CLK_LDB_DI1_PODF 78
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#define IMX6QDL_CLK_IPU1_DI0_PRE 79
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#define IMX6QDL_CLK_IPU1_DI1_PRE 80
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#define IMX6QDL_CLK_IPU2_DI0_PRE 81
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#define IMX6QDL_CLK_IPU2_DI1_PRE 82
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#define IMX6QDL_CLK_HSI_TX_PODF 83
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#define IMX6QDL_CLK_SSI1_PRED 84
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#define IMX6QDL_CLK_SSI1_PODF 85
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#define IMX6QDL_CLK_SSI2_PRED 86
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#define IMX6QDL_CLK_SSI2_PODF 87
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#define IMX6QDL_CLK_SSI3_PRED 88
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#define IMX6QDL_CLK_SSI3_PODF 89
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#define IMX6QDL_CLK_UART_SERIAL_PODF 90
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#define IMX6QDL_CLK_USDHC1_PODF 91
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#define IMX6QDL_CLK_USDHC2_PODF 92
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#define IMX6QDL_CLK_USDHC3_PODF 93
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#define IMX6QDL_CLK_USDHC4_PODF 94
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#define IMX6QDL_CLK_ENFC_PRED 95
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#define IMX6QDL_CLK_ENFC_PODF 96
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#define IMX6QDL_CLK_EIM_PODF 97
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#define IMX6QDL_CLK_EIM_SLOW_PODF 98
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#define IMX6QDL_CLK_VPU_AXI_PODF 99
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#define IMX6QDL_CLK_CKO1_PODF 100
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#define IMX6QDL_CLK_AXI 101
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#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102
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#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103
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#define IMX6QDL_CLK_ARM 104
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#define IMX6QDL_CLK_AHB 105
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#define IMX6QDL_CLK_APBH_DMA 106
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#define IMX6QDL_CLK_ASRC 107
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#define IMX6QDL_CLK_CAN1_IPG 108
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#define IMX6QDL_CLK_CAN1_SERIAL 109
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#define IMX6QDL_CLK_CAN2_IPG 110
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#define IMX6QDL_CLK_CAN2_SERIAL 111
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#define IMX6QDL_CLK_ECSPI1 112
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#define IMX6QDL_CLK_ECSPI2 113
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#define IMX6QDL_CLK_ECSPI3 114
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#define IMX6QDL_CLK_ECSPI4 115
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#define IMX6Q_CLK_ECSPI5 116
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#define IMX6DL_CLK_I2C4 116
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#define IMX6QDL_CLK_ENET 117
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#define IMX6QDL_CLK_ESAI_EXTAL 118
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#define IMX6QDL_CLK_GPT_IPG 119
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#define IMX6QDL_CLK_GPT_IPG_PER 120
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#define IMX6QDL_CLK_GPU2D_CORE 121
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#define IMX6QDL_CLK_GPU3D_CORE 122
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#define IMX6QDL_CLK_HDMI_IAHB 123
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#define IMX6QDL_CLK_HDMI_ISFR 124
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#define IMX6QDL_CLK_I2C1 125
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#define IMX6QDL_CLK_I2C2 126
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#define IMX6QDL_CLK_I2C3 127
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#define IMX6QDL_CLK_IIM 128
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#define IMX6QDL_CLK_ENFC 129
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#define IMX6QDL_CLK_IPU1 130
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#define IMX6QDL_CLK_IPU1_DI0 131
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#define IMX6QDL_CLK_IPU1_DI1 132
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#define IMX6QDL_CLK_IPU2 133
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#define IMX6QDL_CLK_IPU2_DI0 134
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#define IMX6QDL_CLK_LDB_DI0 135
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#define IMX6QDL_CLK_LDB_DI1 136
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#define IMX6QDL_CLK_IPU2_DI1 137
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#define IMX6QDL_CLK_HSI_TX 138
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#define IMX6QDL_CLK_MLB 139
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#define IMX6QDL_CLK_MMDC_CH0_AXI 140
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#define IMX6QDL_CLK_MMDC_CH1_AXI 141
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#define IMX6QDL_CLK_OCRAM 142
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#define IMX6QDL_CLK_OPENVG_AXI 143
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#define IMX6QDL_CLK_PCIE_AXI 144
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#define IMX6QDL_CLK_PWM1 145
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#define IMX6QDL_CLK_PWM2 146
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#define IMX6QDL_CLK_PWM3 147
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#define IMX6QDL_CLK_PWM4 148
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#define IMX6QDL_CLK_PER1_BCH 149
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#define IMX6QDL_CLK_GPMI_BCH_APB 150
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#define IMX6QDL_CLK_GPMI_BCH 151
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#define IMX6QDL_CLK_GPMI_IO 152
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#define IMX6QDL_CLK_GPMI_APB 153
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#define IMX6QDL_CLK_SATA 154
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#define IMX6QDL_CLK_SDMA 155
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#define IMX6QDL_CLK_SPBA 156
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#define IMX6QDL_CLK_SSI1 157
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#define IMX6QDL_CLK_SSI2 158
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#define IMX6QDL_CLK_SSI3 159
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#define IMX6QDL_CLK_UART_IPG 160
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#define IMX6QDL_CLK_UART_SERIAL 161
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#define IMX6QDL_CLK_USBOH3 162
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#define IMX6QDL_CLK_USDHC1 163
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#define IMX6QDL_CLK_USDHC2 164
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#define IMX6QDL_CLK_USDHC3 165
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#define IMX6QDL_CLK_USDHC4 166
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#define IMX6QDL_CLK_VDO_AXI 167
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#define IMX6QDL_CLK_VPU_AXI 168
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#define IMX6QDL_CLK_CKO1 169
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#define IMX6QDL_CLK_PLL1_SYS 170
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#define IMX6QDL_CLK_PLL2_BUS 171
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#define IMX6QDL_CLK_PLL3_USB_OTG 172
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#define IMX6QDL_CLK_PLL4_AUDIO 173
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#define IMX6QDL_CLK_PLL5_VIDEO 174
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#define IMX6QDL_CLK_PLL8_MLB 175
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#define IMX6QDL_CLK_PLL7_USB_HOST 176
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#define IMX6QDL_CLK_PLL6_ENET 177
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#define IMX6QDL_CLK_SSI1_IPG 178
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#define IMX6QDL_CLK_SSI2_IPG 179
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#define IMX6QDL_CLK_SSI3_IPG 180
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#define IMX6QDL_CLK_ROM 181
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#define IMX6QDL_CLK_USBPHY1 182
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#define IMX6QDL_CLK_USBPHY2 183
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#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184
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#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185
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#define IMX6QDL_CLK_SATA_REF 186
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#define IMX6QDL_CLK_SATA_REF_100M 187
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#define IMX6QDL_CLK_PCIE_REF 188
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#define IMX6QDL_CLK_PCIE_REF_125M 189
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#define IMX6QDL_CLK_ENET_REF 190
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#define IMX6QDL_CLK_USBPHY1_GATE 191
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#define IMX6QDL_CLK_USBPHY2_GATE 192
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#define IMX6QDL_CLK_PLL4_POST_DIV 193
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#define IMX6QDL_CLK_PLL5_POST_DIV 194
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#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195
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#define IMX6QDL_CLK_EIM_SLOW 196
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#define IMX6QDL_CLK_SPDIF 197
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#define IMX6QDL_CLK_CKO2_SEL 198
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#define IMX6QDL_CLK_CKO2_PODF 199
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#define IMX6QDL_CLK_CKO2 200
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#define IMX6QDL_CLK_CKO 201
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#define IMX6QDL_CLK_VDOA 202
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#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203
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#define IMX6QDL_CLK_LVDS1_SEL 204
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#define IMX6QDL_CLK_LVDS2_SEL 205
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#define IMX6QDL_CLK_LVDS1_GATE 206
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#define IMX6QDL_CLK_LVDS2_GATE 207
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#define IMX6QDL_CLK_ESAI_IPG 208
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#define IMX6QDL_CLK_ESAI_MEM 209
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#define IMX6QDL_CLK_ASRC_IPG 210
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#define IMX6QDL_CLK_ASRC_MEM 211
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#define IMX6QDL_CLK_LVDS1_IN 212
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#define IMX6QDL_CLK_LVDS2_IN 213
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#define IMX6QDL_CLK_ANACLK1 214
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#define IMX6QDL_CLK_ANACLK2 215
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#define IMX6QDL_PLL1_BYPASS_SRC 216
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#define IMX6QDL_PLL2_BYPASS_SRC 217
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#define IMX6QDL_PLL3_BYPASS_SRC 218
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#define IMX6QDL_PLL4_BYPASS_SRC 219
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#define IMX6QDL_PLL5_BYPASS_SRC 220
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#define IMX6QDL_PLL6_BYPASS_SRC 221
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#define IMX6QDL_PLL7_BYPASS_SRC 222
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#define IMX6QDL_CLK_PLL1 223
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#define IMX6QDL_CLK_PLL2 224
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#define IMX6QDL_CLK_PLL3 225
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#define IMX6QDL_CLK_PLL4 226
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#define IMX6QDL_CLK_PLL5 227
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#define IMX6QDL_CLK_PLL6 228
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#define IMX6QDL_CLK_PLL7 229
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#define IMX6QDL_PLL1_BYPASS 230
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#define IMX6QDL_PLL2_BYPASS 231
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#define IMX6QDL_PLL3_BYPASS 232
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#define IMX6QDL_PLL4_BYPASS 233
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#define IMX6QDL_PLL5_BYPASS 234
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#define IMX6QDL_PLL6_BYPASS 235
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#define IMX6QDL_PLL7_BYPASS 236
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#define IMX6QDL_CLK_GPT_3M 237
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#define IMX6QDL_CLK_VIDEO_27M 238
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#define IMX6QDL_CLK_MIPI_CORE_CFG 239
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#define IMX6QDL_CLK_MIPI_IPG 240
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#define IMX6QDL_CLK_END 241
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#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
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