core:
- uapi: error out EBUSY when existing master
- uapi: rework SET/DROP MASTER permission handling
- remove drm_pci.h
- drm_pci* are now legacy
- introduced managed DRM resources
- subclassing support for drm_framebuffer
- simple encoder helper
- edid improvements
- vblank + writeback documentation improved
- drm/mm - optimise tree searches
- port drivers to use devm_drm_dev_alloc
dma-buf:
- add flag for p2p buffer support
mst:
- ACT timeout improvements
- remove drm_dp_mst_has_audio
- don't use 2nd TX slot - spec recommends against it
bridge:
- dw-hdmi various improvements
- chrontel ch7033 support
- fix stack issues with old gcc
hdmi:
- add unpack function for drm infoframe
fbdev:
- misc fbdev driver fixes
i915:
- uapi: global sseu pinning
- uapi: OA buffer polling
- uapi: remove generated perf code
- uapi: per-engine default property values in sysfs
- Tigerlake GEN12 enabled.
- Lots of gem refactoring
- Tigerlake enablement patches
- move to drm_device logging
- Icelake gamma HW readout
- push MST link retrain to hotplug work
- bandwidth atomic helpers
- ICL fixes
- RPS/GT refactoring
- Cherryview full-ppgtt support
- i915 locking guidelines documented
- require linear fb stride to be 512 multiple on gen9
- Tigerlake SAGV support
amdgpu:
- uapi: encrypted GPU memory handling
- uapi: add MEM_SYNC IB flag
- p2p dma-buf support
- export VRAM dma-bufs
- FRU chip access support
- RAS/SR-IOV updates
- Powerplay locking fixes
- VCN DPG (powergating) enablement
- GFX10 clockgating fixes
- DC fixes
- GPU reset fixes
- navi SDMA fix
- expose FP16 for modesetting
- DP 1.4 compliance fixes
- gfx10 soft recovery
- Improved Critical Thermal Faults handling
- resizable BAR on gmc10
amdkfd:
- uapi: GWS resource management
- track GPU memory per process
- report PCI domain in topology
radeon:
- safe reg list generator fixes
nouveau:
- HD audio fixes on recent systems
- vGPU detection (fail probe if we're on one, for now)
- Interlaced mode fixes (mostly avoidance on Turing, which doesn't support it)
- SVM improvements/fixes
- NVIDIA format modifier support
- Misc other fixes.
adv7511:
- HDMI SPDIF support
ast:
- allocate crtc state size
- fix double assignment
- fix suspend
bochs:
- drop connector register
cirrus:
- move to tiny drivers.
exynos:
- fix imported dma-buf mapping
- enable runtime PM
- fixes and cleanups
mediatek:
- DPI pin mode swap
- config mipi_tx current/impedance
lima:
- devfreq + cooling device support
- task handling improvements
- runtime PM support
pl111:
- vexpress init improvements
- fix module auto-load
rcar-du:
- DT bindings conversion to YAML
- Planes zpos sanity check and fix
- MAINTAINERS entry for LVDS panel driver
mcde:
- fix return value
mgag200:
- use managed config init
stm:
- read endpoints from DT
vboxvideo:
- use PCI managed functions
- drop WC mtrr
vkms:
- enable cursor by default
rockchip:
- afbc support
virtio:
- various cleanups
qxl:
- fix cursor notify port
hisilicon:
- 128-byte stride alignment fix
sun4i:
- improved format handling
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJe1edsAAoJEAx081l5xIa+bKEQAJAZv/8OMM2rx+p+GyKgrNpl
ihTX/oyToy8dw97s1kWF7V5kKU+qjF8aWlKoPS0xovzaMAzYSFz9FRNEUgqtTXMI
zIAzSXioqP21oL9/ZTHcXDULtz8Gk3uiPomgXMWLlNBdt3X5qvCwsmPRIYSwG0GJ
00VCvxDbVxGSM3wzcvbfyRwHCq3SrFvIusXv5jHnnxEFGH0C7Mj2/FLYMKLNjvli
Q8VEI2wQPZj1QdA8fLFVneIQsR6YUSko9OfFMANP8VJGpPMnUkvVxTJ5ACGJspvn
U/h6NYqJeUU2Y3BSKqtjIC3a1LY51tp5tL9q4H9TD1hqMckt6F2V7T2IeFU8i6+V
YzUsSiT4q1xB+uiFVcgopx2hyIp8INOEyWrVdYgw2JviROeRD+pDHvJd13ZNMnTe
GvLWQ/PfBFrcz8eligjiYjOf66ZTU+j/rivaOBFyrs9gdlsaEW2QRurFrcNX+0lZ
kDbLsIFjhYnPXsvHP87x4BuQCKQIEh8wWuxXuJjunBPdqVrJyltZWbBiKO571b5/
BtX6xj6ztUOffR2RdiVanzY546I2hEi7SHMUuWnMqXsOV46GBN0QvlpZad/47n9x
ZUy8HDDD0/qWuGwvPOJGIeAnUteWge9AhWXTeN5+1h5m+QEOzYkPKqC3Hp8TW1pM
gToTWgAhnu731fhzLWyt
=H7IS
-----END PGP SIGNATURE-----
Merge tag 'drm-next-2020-06-02' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie:
"Highlights:
- Core DRM had a lot of refactoring around managed drm resources to
make drivers simpler.
- Intel Tigerlake support is on by default
- amdgpu now support p2p PCI buffer sharing and encrypted GPU memory
Details:
core:
- uapi: error out EBUSY when existing master
- uapi: rework SET/DROP MASTER permission handling
- remove drm_pci.h
- drm_pci* are now legacy
- introduced managed DRM resources
- subclassing support for drm_framebuffer
- simple encoder helper
- edid improvements
- vblank + writeback documentation improved
- drm/mm - optimise tree searches
- port drivers to use devm_drm_dev_alloc
dma-buf:
- add flag for p2p buffer support
mst:
- ACT timeout improvements
- remove drm_dp_mst_has_audio
- don't use 2nd TX slot - spec recommends against it
bridge:
- dw-hdmi various improvements
- chrontel ch7033 support
- fix stack issues with old gcc
hdmi:
- add unpack function for drm infoframe
fbdev:
- misc fbdev driver fixes
i915:
- uapi: global sseu pinning
- uapi: OA buffer polling
- uapi: remove generated perf code
- uapi: per-engine default property values in sysfs
- Tigerlake GEN12 enabled.
- Lots of gem refactoring
- Tigerlake enablement patches
- move to drm_device logging
- Icelake gamma HW readout
- push MST link retrain to hotplug work
- bandwidth atomic helpers
- ICL fixes
- RPS/GT refactoring
- Cherryview full-ppgtt support
- i915 locking guidelines documented
- require linear fb stride to be 512 multiple on gen9
- Tigerlake SAGV support
amdgpu:
- uapi: encrypted GPU memory handling
- uapi: add MEM_SYNC IB flag
- p2p dma-buf support
- export VRAM dma-bufs
- FRU chip access support
- RAS/SR-IOV updates
- Powerplay locking fixes
- VCN DPG (powergating) enablement
- GFX10 clockgating fixes
- DC fixes
- GPU reset fixes
- navi SDMA fix
- expose FP16 for modesetting
- DP 1.4 compliance fixes
- gfx10 soft recovery
- Improved Critical Thermal Faults handling
- resizable BAR on gmc10
amdkfd:
- uapi: GWS resource management
- track GPU memory per process
- report PCI domain in topology
radeon:
- safe reg list generator fixes
nouveau:
- HD audio fixes on recent systems
- vGPU detection (fail probe if we're on one, for now)
- Interlaced mode fixes (mostly avoidance on Turing, which doesn't support it)
- SVM improvements/fixes
- NVIDIA format modifier support
- Misc other fixes.
adv7511:
- HDMI SPDIF support
ast:
- allocate crtc state size
- fix double assignment
- fix suspend
bochs:
- drop connector register
cirrus:
- move to tiny drivers.
exynos:
- fix imported dma-buf mapping
- enable runtime PM
- fixes and cleanups
mediatek:
- DPI pin mode swap
- config mipi_tx current/impedance
lima:
- devfreq + cooling device support
- task handling improvements
- runtime PM support
pl111:
- vexpress init improvements
- fix module auto-load
rcar-du:
- DT bindings conversion to YAML
- Planes zpos sanity check and fix
- MAINTAINERS entry for LVDS panel driver
mcde:
- fix return value
mgag200:
- use managed config init
stm:
- read endpoints from DT
vboxvideo:
- use PCI managed functions
- drop WC mtrr
vkms:
- enable cursor by default
rockchip:
- afbc support
virtio:
- various cleanups
qxl:
- fix cursor notify port
hisilicon:
- 128-byte stride alignment fix
sun4i:
- improved format handling"
* tag 'drm-next-2020-06-02' of git://anongit.freedesktop.org/drm/drm: (1401 commits)
drm/amd/display: Fix potential integer wraparound resulting in a hang
drm/amd/display: drop cursor position check in atomic test
drm/amdgpu: fix device attribute node create failed with multi gpu
drm/nouveau: use correct conflicting framebuffer API
drm/vblank: Fix -Wformat compile warnings on some arches
drm/amdgpu: Sync with VM root BO when switching VM to CPU update mode
drm/amd/display: Handle GPU reset for DC block
drm/amdgpu: add apu flags (v2)
drm/amd/powerpay: Disable gfxoff when setting manual mode on picasso and raven
drm/amdgpu: fix pm sysfs node handling (v2)
drm/amdgpu: move gpu_info parsing after common early init
drm/amdgpu: move discovery gfx config fetching
drm/nouveau/dispnv50: fix runtime pm imbalance on error
drm/nouveau: fix runtime pm imbalance on error
drm/nouveau: fix runtime pm imbalance on error
drm/nouveau/debugfs: fix runtime pm imbalance on error
drm/nouveau/nouveau/hmm: fix migrate zero page to GPU
drm/nouveau/nouveau/hmm: fix nouveau_dmem_chunk allocations
drm/nouveau/kms/nv50-: Share DP SST mode_valid() handling with MST
drm/nouveau/kms/nv50-: Move 8BPC limit for MST into nv50_mstc_get_modes()
...
273 lines
6.8 KiB
C
273 lines
6.8 KiB
C
/*
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* Copyright (C) 2015 Red Hat, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <drm/drm_file.h>
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#include <drm/drm_fourcc.h>
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#include "virtgpu_drv.h"
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static int virtio_gpu_gem_create(struct drm_file *file,
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struct drm_device *dev,
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struct virtio_gpu_object_params *params,
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struct drm_gem_object **obj_p,
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uint32_t *handle_p)
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{
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct virtio_gpu_object *obj;
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int ret;
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u32 handle;
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if (vgdev->has_virgl_3d)
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virtio_gpu_create_context(dev, file);
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ret = virtio_gpu_object_create(vgdev, params, &obj, NULL);
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if (ret < 0)
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return ret;
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ret = drm_gem_handle_create(file, &obj->base.base, &handle);
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if (ret) {
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drm_gem_object_release(&obj->base.base);
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return ret;
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}
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*obj_p = &obj->base.base;
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/* drop reference from allocate - handle holds it now */
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drm_gem_object_put_unlocked(&obj->base.base);
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*handle_p = handle;
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return 0;
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}
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int virtio_gpu_mode_dumb_create(struct drm_file *file_priv,
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struct drm_device *dev,
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struct drm_mode_create_dumb *args)
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{
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struct drm_gem_object *gobj;
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struct virtio_gpu_object_params params = { 0 };
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int ret;
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uint32_t pitch;
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if (args->bpp != 32)
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return -EINVAL;
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pitch = args->width * 4;
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args->size = pitch * args->height;
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args->size = ALIGN(args->size, PAGE_SIZE);
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params.format = virtio_gpu_translate_format(DRM_FORMAT_HOST_XRGB8888);
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params.width = args->width;
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params.height = args->height;
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params.size = args->size;
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params.dumb = true;
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ret = virtio_gpu_gem_create(file_priv, dev, ¶ms, &gobj,
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&args->handle);
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if (ret)
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goto fail;
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args->pitch = pitch;
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return ret;
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fail:
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return ret;
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}
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int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv,
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struct drm_device *dev,
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uint32_t handle, uint64_t *offset_p)
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{
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struct drm_gem_object *gobj;
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BUG_ON(!offset_p);
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gobj = drm_gem_object_lookup(file_priv, handle);
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if (gobj == NULL)
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return -ENOENT;
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*offset_p = drm_vma_node_offset_addr(&gobj->vma_node);
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drm_gem_object_put_unlocked(gobj);
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return 0;
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}
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int virtio_gpu_gem_object_open(struct drm_gem_object *obj,
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struct drm_file *file)
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{
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struct virtio_gpu_device *vgdev = obj->dev->dev_private;
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struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
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struct virtio_gpu_object_array *objs;
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if (!vgdev->has_virgl_3d)
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goto out_notify;
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objs = virtio_gpu_array_alloc(1);
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if (!objs)
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return -ENOMEM;
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virtio_gpu_array_add_obj(objs, obj);
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virtio_gpu_cmd_context_attach_resource(vgdev, vfpriv->ctx_id,
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objs);
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out_notify:
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virtio_gpu_notify(vgdev);
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return 0;
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}
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void virtio_gpu_gem_object_close(struct drm_gem_object *obj,
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struct drm_file *file)
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{
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struct virtio_gpu_device *vgdev = obj->dev->dev_private;
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struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
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struct virtio_gpu_object_array *objs;
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if (!vgdev->has_virgl_3d)
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return;
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objs = virtio_gpu_array_alloc(1);
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if (!objs)
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return;
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virtio_gpu_array_add_obj(objs, obj);
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virtio_gpu_cmd_context_detach_resource(vgdev, vfpriv->ctx_id,
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objs);
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virtio_gpu_notify(vgdev);
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}
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struct virtio_gpu_object_array *virtio_gpu_array_alloc(u32 nents)
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{
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struct virtio_gpu_object_array *objs;
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size_t size = sizeof(*objs) + sizeof(objs->objs[0]) * nents;
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objs = kmalloc(size, GFP_KERNEL);
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if (!objs)
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return NULL;
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objs->nents = 0;
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objs->total = nents;
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return objs;
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}
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static void virtio_gpu_array_free(struct virtio_gpu_object_array *objs)
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{
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kfree(objs);
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}
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struct virtio_gpu_object_array*
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virtio_gpu_array_from_handles(struct drm_file *drm_file, u32 *handles, u32 nents)
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{
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struct virtio_gpu_object_array *objs;
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u32 i;
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objs = virtio_gpu_array_alloc(nents);
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if (!objs)
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return NULL;
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for (i = 0; i < nents; i++) {
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objs->objs[i] = drm_gem_object_lookup(drm_file, handles[i]);
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if (!objs->objs[i]) {
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objs->nents = i;
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virtio_gpu_array_put_free(objs);
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return NULL;
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}
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}
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objs->nents = i;
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return objs;
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}
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void virtio_gpu_array_add_obj(struct virtio_gpu_object_array *objs,
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struct drm_gem_object *obj)
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{
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if (WARN_ON_ONCE(objs->nents == objs->total))
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return;
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drm_gem_object_get(obj);
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objs->objs[objs->nents] = obj;
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objs->nents++;
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}
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int virtio_gpu_array_lock_resv(struct virtio_gpu_object_array *objs)
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{
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int ret;
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if (objs->nents == 1) {
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ret = dma_resv_lock_interruptible(objs->objs[0]->resv, NULL);
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} else {
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ret = drm_gem_lock_reservations(objs->objs, objs->nents,
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&objs->ticket);
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}
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return ret;
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}
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void virtio_gpu_array_unlock_resv(struct virtio_gpu_object_array *objs)
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{
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if (objs->nents == 1) {
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dma_resv_unlock(objs->objs[0]->resv);
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} else {
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drm_gem_unlock_reservations(objs->objs, objs->nents,
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&objs->ticket);
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}
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}
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void virtio_gpu_array_add_fence(struct virtio_gpu_object_array *objs,
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struct dma_fence *fence)
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{
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int i;
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for (i = 0; i < objs->nents; i++)
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dma_resv_add_excl_fence(objs->objs[i]->resv, fence);
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}
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void virtio_gpu_array_put_free(struct virtio_gpu_object_array *objs)
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{
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u32 i;
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for (i = 0; i < objs->nents; i++)
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drm_gem_object_put_unlocked(objs->objs[i]);
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virtio_gpu_array_free(objs);
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}
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void virtio_gpu_array_put_free_delayed(struct virtio_gpu_device *vgdev,
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struct virtio_gpu_object_array *objs)
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{
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spin_lock(&vgdev->obj_free_lock);
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list_add_tail(&objs->next, &vgdev->obj_free_list);
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spin_unlock(&vgdev->obj_free_lock);
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schedule_work(&vgdev->obj_free_work);
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}
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void virtio_gpu_array_put_free_work(struct work_struct *work)
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{
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struct virtio_gpu_device *vgdev =
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container_of(work, struct virtio_gpu_device, obj_free_work);
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struct virtio_gpu_object_array *objs;
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spin_lock(&vgdev->obj_free_lock);
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while (!list_empty(&vgdev->obj_free_list)) {
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objs = list_first_entry(&vgdev->obj_free_list,
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struct virtio_gpu_object_array, next);
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list_del(&objs->next);
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spin_unlock(&vgdev->obj_free_lock);
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virtio_gpu_array_put_free(objs);
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spin_lock(&vgdev->obj_free_lock);
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}
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spin_unlock(&vgdev->obj_free_lock);
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}
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