d7194cf6b8
The dc_gamma in dc_surface will be programmed to the input LUT if provided. If dc_gamma is not provided in dc_surface regamma may be used to emulate gamma. Some refactor and cleanup included as well. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
415 lines
16 KiB
C
415 lines
16 KiB
C
/* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_OPP_DCE_H__
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#define __DC_OPP_DCE_H__
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#include "dc_types.h"
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#include "opp.h"
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#include "core_types.h"
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#define FROM_DCE11_OPP(opp)\
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container_of(opp, struct dce110_opp, base)
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enum dce110_opp_reg_type {
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DCE110_OPP_REG_DCP = 0,
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DCE110_OPP_REG_DCFE,
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DCE110_OPP_REG_FMT,
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DCE110_OPP_REG_MAX
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};
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#define OPP_COMMON_REG_LIST_BASE(id) \
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SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \
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SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \
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SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \
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SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \
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SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \
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SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \
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SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \
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SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \
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SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \
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SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \
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SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \
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SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \
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SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \
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SRI(REGAMMA_LUT_INDEX, DCP, id), \
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SRI(REGAMMA_LUT_DATA, DCP, id), \
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SRI(REGAMMA_CONTROL, DCP, id), \
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SRI(OUTPUT_CSC_C11_C12, DCP, id), \
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SRI(OUTPUT_CSC_C13_C14, DCP, id), \
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SRI(OUTPUT_CSC_C21_C22, DCP, id), \
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SRI(OUTPUT_CSC_C23_C24, DCP, id), \
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SRI(OUTPUT_CSC_C31_C32, DCP, id), \
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SRI(OUTPUT_CSC_C33_C34, DCP, id), \
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SRI(OUTPUT_CSC_CONTROL, DCP, id), \
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SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
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SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
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SRI(FMT_CONTROL, FMT, id), \
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SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
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SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
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SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
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SRI(FMT_CLAMP_CNTL, FMT, id), \
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SRI(FMT_CLAMP_COMPONENT_R, FMT, id), \
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SRI(FMT_CLAMP_COMPONENT_G, FMT, id), \
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SRI(FMT_CLAMP_COMPONENT_B, FMT, id)
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#define OPP_DCE_80_REG_LIST(id) \
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OPP_COMMON_REG_LIST_BASE(id), \
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SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id), \
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SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
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SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
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SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)
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#define OPP_DCE_100_REG_LIST(id) \
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OPP_COMMON_REG_LIST_BASE(id), \
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SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
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SRI(DCFE_MEM_PWR_STATUS, CRTC, id), \
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SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
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SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
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SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)
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#define OPP_DCE_110_REG_LIST(id) \
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OPP_COMMON_REG_LIST_BASE(id), \
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SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
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SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \
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SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
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SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
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SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)
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#define OPP_DCE_112_REG_LIST(id) \
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OPP_COMMON_REG_LIST_BASE(id), \
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SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
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SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \
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SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
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SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
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SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \
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SRI(CONTROL, FMT_MEMORY, id)
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#define OPP_SF(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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#define OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
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OPP_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\
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OPP_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\
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OPP_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\
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OPP_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\
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OPP_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\
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OPP_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\
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OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\
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OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
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OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\
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OPP_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
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OPP_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\
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OPP_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\
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OPP_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\
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OPP_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\
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OPP_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
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OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\
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OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\
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OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\
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OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\
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OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\
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OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\
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OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\
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OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\
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OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\
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OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\
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OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\
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OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
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OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\
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OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\
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OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\
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OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
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OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\
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OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\
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OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\
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OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\
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OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\
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OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\
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OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\
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OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\
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OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\
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OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\
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OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\
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OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\
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OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\
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OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\
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OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\
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OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\
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OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\
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OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\
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OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh)
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#define OPP_COMMON_MASK_SH_LIST_DCE_110(mask_sh)\
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OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
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OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
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OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
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OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\
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OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
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OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh)
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#define OPP_COMMON_MASK_SH_LIST_DCE_100(mask_sh)\
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OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
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OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
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OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
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OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\
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OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
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OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh)
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#define OPP_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\
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OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
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OPP_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
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OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
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OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\
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OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\
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OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\
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OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\
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OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\
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OPP_SF(FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh),\
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OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
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OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh)
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#define OPP_COMMON_MASK_SH_LIST_DCE_80(mask_sh)\
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OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
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OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\
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OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\
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OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh)
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#define OPP_REG_FIELD_LIST(type) \
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type DCP_REGAMMA_MEM_PWR_DIS; \
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type DCP_LUT_MEM_PWR_DIS; \
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type REGAMMA_LUT_LIGHT_SLEEP_DIS; \
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type DCP_LUT_LIGHT_SLEEP_DIS; \
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type REGAMMA_CNTLA_EXP_REGION_START; \
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type REGAMMA_CNTLA_EXP_REGION_START_SEGMENT; \
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type REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE; \
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type REGAMMA_CNTLA_EXP_REGION_END; \
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type REGAMMA_CNTLA_EXP_REGION_END_BASE; \
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type REGAMMA_CNTLA_EXP_REGION_END_SLOPE; \
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type REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET; \
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type REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS; \
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type REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET; \
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type REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS; \
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type DCP_REGAMMA_MEM_PWR_STATE; \
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type REGAMMA_LUT_MEM_PWR_STATE; \
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type REGAMMA_LUT_WRITE_EN_MASK; \
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type GRPH_REGAMMA_MODE; \
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type OUTPUT_CSC_C11; \
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type OUTPUT_CSC_C12; \
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type OUTPUT_CSC_GRPH_MODE; \
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type FMT_DYNAMIC_EXP_EN; \
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type FMT_DYNAMIC_EXP_MODE; \
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type FMT_TRUNCATE_EN; \
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type FMT_TRUNCATE_DEPTH; \
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type FMT_TRUNCATE_MODE; \
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type FMT_SPATIAL_DITHER_EN; \
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type FMT_SPATIAL_DITHER_DEPTH; \
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type FMT_SPATIAL_DITHER_MODE; \
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type FMT_TEMPORAL_DITHER_EN; \
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type FMT_TEMPORAL_DITHER_RESET; \
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type FMT_TEMPORAL_DITHER_OFFSET; \
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type FMT_TEMPORAL_DITHER_DEPTH; \
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type FMT_TEMPORAL_LEVEL; \
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type FMT_25FRC_SEL; \
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type FMT_50FRC_SEL; \
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type FMT_75FRC_SEL; \
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type FMT_HIGHPASS_RANDOM_ENABLE; \
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type FMT_FRAME_RANDOM_ENABLE; \
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type FMT_RGB_RANDOM_ENABLE; \
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type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \
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type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \
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type FMT_RAND_R_SEED; \
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type FMT_RAND_G_SEED; \
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type FMT_RAND_B_SEED; \
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type FMT420_MEM0_SOURCE_SEL; \
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type FMT420_MEM0_PWR_FORCE; \
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type FMT_SRC_SELECT; \
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type FMT_420_PIXEL_PHASE_LOCKED_CLEAR; \
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type FMT_420_PIXEL_PHASE_LOCKED; \
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type FMT_CLAMP_DATA_EN; \
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type FMT_CLAMP_COLOR_FORMAT; \
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type FMT_CLAMP_LOWER_R; \
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type FMT_CLAMP_UPPER_R; \
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type FMT_CLAMP_LOWER_G; \
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type FMT_CLAMP_UPPER_G; \
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type FMT_CLAMP_LOWER_B; \
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type FMT_CLAMP_UPPER_B; \
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type FMT_PIXEL_ENCODING; \
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type FMT_SUBSAMPLING_ORDER; \
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type FMT_SUBSAMPLING_MODE; \
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type FMT_CBCR_BIT_REDUCTION_BYPASS;\
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struct dce_opp_shift {
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OPP_REG_FIELD_LIST(uint8_t)
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};
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struct dce_opp_mask {
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OPP_REG_FIELD_LIST(uint32_t)
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};
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struct dce_opp_registers {
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uint32_t DCFE_MEM_PWR_CTRL;
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uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL;
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uint32_t REGAMMA_CNTLA_START_CNTL;
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uint32_t REGAMMA_CNTLA_SLOPE_CNTL;
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uint32_t REGAMMA_CNTLA_END_CNTL1;
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uint32_t REGAMMA_CNTLA_END_CNTL2;
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uint32_t REGAMMA_CNTLA_REGION_0_1;
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uint32_t REGAMMA_CNTLA_REGION_2_3;
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uint32_t REGAMMA_CNTLA_REGION_4_5;
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uint32_t REGAMMA_CNTLA_REGION_6_7;
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uint32_t REGAMMA_CNTLA_REGION_8_9;
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uint32_t REGAMMA_CNTLA_REGION_10_11;
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uint32_t REGAMMA_CNTLA_REGION_12_13;
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uint32_t REGAMMA_CNTLA_REGION_14_15;
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uint32_t REGAMMA_LUT_WRITE_EN_MASK;
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uint32_t REGAMMA_LUT_INDEX;
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uint32_t DCFE_MEM_PWR_STATUS;
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uint32_t REGAMMA_LUT_DATA;
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uint32_t REGAMMA_CONTROL;
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uint32_t OUTPUT_CSC_C11_C12;
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uint32_t OUTPUT_CSC_C13_C14;
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uint32_t OUTPUT_CSC_C21_C22;
|
|
uint32_t OUTPUT_CSC_C23_C24;
|
|
uint32_t OUTPUT_CSC_C31_C32;
|
|
uint32_t OUTPUT_CSC_C33_C34;
|
|
uint32_t OUTPUT_CSC_CONTROL;
|
|
uint32_t FMT_DYNAMIC_EXP_CNTL;
|
|
uint32_t FMT_BIT_DEPTH_CONTROL;
|
|
uint32_t FMT_CONTROL;
|
|
uint32_t FMT_DITHER_RAND_R_SEED;
|
|
uint32_t FMT_DITHER_RAND_G_SEED;
|
|
uint32_t FMT_DITHER_RAND_B_SEED;
|
|
uint32_t FMT_TEMPORAL_DITHER_PATTERN_CONTROL;
|
|
uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX;
|
|
uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX;
|
|
uint32_t CONTROL;
|
|
uint32_t FMT_CLAMP_CNTL;
|
|
uint32_t FMT_CLAMP_COMPONENT_R;
|
|
uint32_t FMT_CLAMP_COMPONENT_G;
|
|
uint32_t FMT_CLAMP_COMPONENT_B;
|
|
};
|
|
|
|
struct dce110_regamma {
|
|
struct gamma_curve arr_curve_points[16];
|
|
struct curve_points arr_points[3];
|
|
uint32_t hw_points_num;
|
|
struct hw_x_point *coordinates_x;
|
|
struct pwl_result_data *rgb_resulted;
|
|
|
|
/* re-gamma curve */
|
|
struct pwl_float_data_ex *rgb_regamma;
|
|
/* coeff used to map user evenly distributed points
|
|
* to our hardware points (predefined) for gamma 256 */
|
|
struct pixel_gamma_point *coeff128;
|
|
struct pixel_gamma_point *coeff128_oem;
|
|
/* coeff used to map user evenly distributed points
|
|
* to our hardware points (predefined) for gamma 1025 */
|
|
struct pixel_gamma_point *coeff128_dx;
|
|
/* evenly distributed points, gamma 256 software points 0-255 */
|
|
struct gamma_pixel *axis_x_256;
|
|
/* evenly distributed points, gamma 1025 software points 0-1025 */
|
|
struct gamma_pixel *axis_x_1025;
|
|
/* OEM supplied gamma for regamma LUT */
|
|
struct pwl_float_data *rgb_oem;
|
|
/* user supplied gamma */
|
|
struct pwl_float_data *rgb_user;
|
|
uint32_t extra_points;
|
|
bool use_half_points;
|
|
struct fixed31_32 x_max1;
|
|
struct fixed31_32 x_max2;
|
|
struct fixed31_32 x_min;
|
|
struct fixed31_32 divider1;
|
|
struct fixed31_32 divider2;
|
|
struct fixed31_32 divider3;
|
|
};
|
|
|
|
/* OPP RELATED */
|
|
#define TO_DCE110_OPP(opp)\
|
|
container_of(opp, struct dce110_opp, base)
|
|
|
|
struct dce110_opp {
|
|
struct output_pixel_processor base;
|
|
const struct dce_opp_registers *regs;
|
|
const struct dce_opp_shift *opp_shift;
|
|
const struct dce_opp_mask *opp_mask;
|
|
struct dce110_regamma regamma;
|
|
};
|
|
|
|
bool dce110_opp_construct(struct dce110_opp *opp110,
|
|
struct dc_context *ctx,
|
|
uint32_t inst,
|
|
const struct dce_opp_registers *regs,
|
|
const struct dce_opp_shift *opp_shift,
|
|
const struct dce_opp_mask *opp_mask);
|
|
|
|
void dce110_opp_destroy(struct output_pixel_processor **opp);
|
|
|
|
/* REGAMMA RELATED */
|
|
void dce110_opp_power_on_regamma_lut(
|
|
struct output_pixel_processor *opp,
|
|
bool power_on);
|
|
|
|
bool dce110_opp_program_regamma_pwl(
|
|
struct output_pixel_processor *opp,
|
|
const struct pwl_params *params);
|
|
|
|
void dce110_opp_set_regamma_mode(struct output_pixel_processor *opp,
|
|
enum opp_regamma mode);
|
|
|
|
void dce110_opp_set_csc_adjustment(
|
|
struct output_pixel_processor *opp,
|
|
const struct out_csc_color_matrix *tbl_entry);
|
|
|
|
void dce110_opp_set_csc_default(
|
|
struct output_pixel_processor *opp,
|
|
const struct default_adjustment *default_adjust);
|
|
|
|
/* FORMATTER RELATED */
|
|
void dce110_opp_program_bit_depth_reduction(
|
|
struct output_pixel_processor *opp,
|
|
const struct bit_depth_reduction_params *params);
|
|
|
|
void dce110_opp_program_clamping_and_pixel_encoding(
|
|
struct output_pixel_processor *opp,
|
|
const struct clamping_and_pixel_encoding_params *params);
|
|
|
|
void dce110_opp_set_dyn_expansion(
|
|
struct output_pixel_processor *opp,
|
|
enum dc_color_space color_sp,
|
|
enum dc_color_depth color_dpth,
|
|
enum signal_type signal);
|
|
|
|
void dce110_opp_program_fmt(
|
|
struct output_pixel_processor *opp,
|
|
struct bit_depth_reduction_params *fmt_bit_depth,
|
|
struct clamping_and_pixel_encoding_params *clamping);
|
|
|
|
void dce110_opp_set_clamping(
|
|
struct dce110_opp *opp110,
|
|
const struct clamping_and_pixel_encoding_params *params);
|
|
|
|
#endif
|