linux/drivers/gpu/drm/amd/display/dc/inc
Jake Wang 71ae580f31 drm/amd/display: Ensure DCN save after VM setup
[Why]
DM initializes VM context after DMCUB initialization.
This results in loss of DCN_VM_CONTEXT registers after z10.

[How]
Notify DMCUB when VM setup is complete, and have DMCUB
save init registers.

v2: squash in CONFIG_DRM_AMD_DC_DCN3_1 fix

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-16 16:04:24 -04:00
..
hw drm/amd/display: Line Buffer changes 2021-07-21 14:25:58 -04:00
bw_fixed.h
clock_source.h drm/amd/display: Synchronize displays with different timings 2021-02-22 18:05:48 -05:00
compressor.h
core_status.h drm/amd/display: fail instead of div by zero/bugcheck 2020-11-02 15:30:47 -05:00
core_types.h drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN 2021-06-22 16:51:45 -04:00
custom_float.h
dc_link_ddc.h drm/amd/display: Support for DMUB AUX 2021-03-02 14:05:41 -05:00
dc_link_dp.h drm/amd/display: Read LTTPR caps first on bootup 2021-06-15 17:25:41 -04:00
dce_calcs.h
dcn_calc_math.h drm/amd/display: fixup DML dependencies 2020-01-16 14:16:48 -05:00
dcn_calcs.h
hw_sequencer_private.h drm/amd/display: implement workaround for riommu related hang 2021-07-21 14:21:59 -04:00
hw_sequencer.h drm/amd/display: Ensure DCN save after VM setup 2021-08-16 16:04:24 -04:00
link_dpcd.h drm/amd/display: Enforce DPCD Address ranges 2021-06-15 17:25:41 -04:00
link_enc_cfg.h drm/amd/display: Update setting of DP training parameters. 2021-05-10 18:09:53 -04:00
link_hwss.h drm/amd/display: Enforce DPCD Address ranges 2021-06-15 17:25:41 -04:00
reg_helper.h drm/amd/display: Indirect reg read macro with shift and mask 2020-01-16 14:13:53 -05:00
resource.h drm/amd/display: Update link encoder object creation 2021-03-02 14:05:52 -05:00
vm_helper.h