forked from Minki/linux
1338760329
This patch allows booting Kirkwood with the L2 in writeback mode, by reading the WT override bit from the L2 config register and passing that into the Feroceon L2 init routine, instead of assuming that the WT override bit will always be set Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
101 lines
3.1 KiB
C
101 lines
3.1 KiB
C
/*
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* include/asm-arm/arch-kirkwood/kirkwood.h
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*
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* Generic definitions for Marvell Kirkwood SoC flavors:
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* 88F6180, 88F6192 and 88F6281.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_KIRKWOOD_H
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#define __ASM_ARCH_KIRKWOOD_H
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/*
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* Marvell Kirkwood address maps.
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*
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* phys
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* e0000000 PCIe Memory space
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* f1000000 on-chip peripheral registers
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* f2000000 PCIe I/O space
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* f3000000 NAND controller address window
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*
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* virt phys size
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* fee00000 f1000000 1M on-chip peripheral registers
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* fef00000 f2000000 1M PCIe I/O space
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*/
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#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000
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#define KIRKWOOD_NAND_MEM_SIZE SZ_64K /* 1K is sufficient, but 64K
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* is the minimal window size
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*/
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#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
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#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000
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#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000
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#define KIRKWOOD_PCIE_IO_SIZE SZ_1M
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#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
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#define KIRKWOOD_REGS_VIRT_BASE 0xfee00000
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#define KIRKWOOD_REGS_SIZE SZ_1M
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#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
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#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M
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/*
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* MBUS bridge registers.
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*/
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#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
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#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
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#define CPU_RESET 0x00000002
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
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#define SOFT_RESET 0x00000001
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#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
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#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
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#define BRIDGE_INT_TIMER0 0x0002
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#define BRIDGE_INT_TIMER1 0x0004
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#define BRIDGE_INT_TIMER1_CLR (~0x0004)
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#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
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#define IRQ_CAUSE_LOW_OFF 0x0000
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#define IRQ_MASK_LOW_OFF 0x0004
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#define IRQ_CAUSE_HIGH_OFF 0x0010
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#define IRQ_MASK_HIGH_OFF 0x0014
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#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
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#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128)
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#define L2_WRITETHROUGH 0x00000010
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/*
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* Register Map
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*/
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#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
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#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500)
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#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
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#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
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#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030)
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#define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034)
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#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300)
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#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600)
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#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
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#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
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#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
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#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
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#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
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#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
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#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
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#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
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#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
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#define GPIO_MAX 50
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#endif
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