forked from Minki/linux
d175ed2bd6
As is done for UFR, ensure that userland cannot directly manipulate the mode by clearing the UFE bit during boot. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7677/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
1358 lines
33 KiB
C
1358 lines
33 KiB
C
/*
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* Processor capabilities determination functions.
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*
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* Copyright (C) xxxx the Anonymous
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* Copyright (C) 1994 - 2006 Ralf Baechle
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* Copyright (C) 2003, 2004 Maciej W. Rozycki
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* Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/ptrace.h>
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#include <linux/smp.h>
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#include <linux/stddef.h>
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#include <linux/export.h>
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#include <asm/bugs.h>
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#include <asm/cpu.h>
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#include <asm/cpu-type.h>
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#include <asm/fpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/msa.h>
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#include <asm/watch.h>
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#include <asm/elf.h>
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#include <asm/pgtable-bits.h>
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#include <asm/spram.h>
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#include <asm/uaccess.h>
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static int mips_fpu_disabled;
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static int __init fpu_disable(char *s)
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{
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cpu_data[0].options &= ~MIPS_CPU_FPU;
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mips_fpu_disabled = 1;
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return 1;
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}
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__setup("nofpu", fpu_disable);
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int mips_dsp_disabled;
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static int __init dsp_disable(char *s)
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{
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cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
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mips_dsp_disabled = 1;
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return 1;
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}
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__setup("nodsp", dsp_disable);
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static int mips_htw_disabled;
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static int __init htw_disable(char *s)
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{
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mips_htw_disabled = 1;
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cpu_data[0].options &= ~MIPS_CPU_HTW;
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write_c0_pwctl(read_c0_pwctl() &
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~(1 << MIPS_PWCTL_PWEN_SHIFT));
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return 1;
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}
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__setup("nohtw", htw_disable);
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static int mips_ftlb_disabled;
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static int mips_has_ftlb_configured;
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static void set_ftlb_enable(struct cpuinfo_mips *c, int enable);
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static int __init ftlb_disable(char *s)
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{
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unsigned int config4, mmuextdef;
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/*
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* If the core hasn't done any FTLB configuration, there is nothing
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* for us to do here.
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*/
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if (!mips_has_ftlb_configured)
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return 1;
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/* Disable it in the boot cpu */
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set_ftlb_enable(&cpu_data[0], 0);
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back_to_back_c0_hazard();
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config4 = read_c0_config4();
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/* Check that FTLB has been disabled */
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mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
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/* MMUSIZEEXT == VTLB ON, FTLB OFF */
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if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
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/* This should never happen */
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pr_warn("FTLB could not be disabled!\n");
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return 1;
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}
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mips_ftlb_disabled = 1;
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mips_has_ftlb_configured = 0;
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/*
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* noftlb is mainly used for debug purposes so print
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* an informative message instead of using pr_debug()
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*/
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pr_info("FTLB has been disabled\n");
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/*
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* Some of these bits are duplicated in the decode_config4.
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* MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
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* once FTLB has been disabled so undo what decode_config4 did.
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*/
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cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
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cpu_data[0].tlbsizeftlbsets;
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cpu_data[0].tlbsizeftlbsets = 0;
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cpu_data[0].tlbsizeftlbways = 0;
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return 1;
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}
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__setup("noftlb", ftlb_disable);
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static inline void check_errata(void)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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switch (current_cpu_type()) {
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case CPU_34K:
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/*
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* Erratum "RPS May Cause Incorrect Instruction Execution"
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* This code only handles VPE0, any SMP/RTOS code
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* making use of VPE1 will be responsable for that VPE.
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*/
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if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
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write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
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break;
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default:
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break;
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}
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}
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void __init check_bugs32(void)
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{
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check_errata();
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}
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/*
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* Probe whether cpu has config register by trying to play with
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* alternate cache bit and see whether it matters.
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* It's used by cpu_probe to distinguish between R3000A and R3081.
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*/
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static inline int cpu_has_confreg(void)
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{
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#ifdef CONFIG_CPU_R3000
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extern unsigned long r3k_cache_size(unsigned long);
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unsigned long size1, size2;
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unsigned long cfg = read_c0_conf();
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size1 = r3k_cache_size(ST0_ISC);
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write_c0_conf(cfg ^ R30XX_CONF_AC);
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size2 = r3k_cache_size(ST0_ISC);
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write_c0_conf(cfg);
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return size1 != size2;
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#else
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return 0;
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#endif
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}
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static inline void set_elf_platform(int cpu, const char *plat)
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{
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if (cpu == 0)
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__elf_platform = plat;
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}
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/*
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* Get the FPU Implementation/Revision.
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*/
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static inline unsigned long cpu_get_fpu_id(void)
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{
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unsigned long tmp, fpu_id;
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tmp = read_c0_status();
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__enable_fpu(FPU_AS_IS);
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fpu_id = read_32bit_cp1_register(CP1_REVISION);
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write_c0_status(tmp);
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return fpu_id;
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}
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/*
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* Check the CPU has an FPU the official way.
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*/
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static inline int __cpu_has_fpu(void)
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{
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return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
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}
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static inline unsigned long cpu_get_msa_id(void)
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{
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unsigned long status, msa_id;
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status = read_c0_status();
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__enable_fpu(FPU_64BIT);
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enable_msa();
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msa_id = read_msa_ir();
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disable_msa();
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write_c0_status(status);
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return msa_id;
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}
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static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
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{
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#ifdef __NEED_VMBITS_PROBE
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write_c0_entryhi(0x3fffffffffffe000ULL);
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back_to_back_c0_hazard();
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c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
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#endif
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}
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static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
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{
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switch (isa) {
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case MIPS_CPU_ISA_M64R2:
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c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
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case MIPS_CPU_ISA_M64R1:
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c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
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case MIPS_CPU_ISA_V:
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c->isa_level |= MIPS_CPU_ISA_V;
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case MIPS_CPU_ISA_IV:
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c->isa_level |= MIPS_CPU_ISA_IV;
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case MIPS_CPU_ISA_III:
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c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
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break;
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case MIPS_CPU_ISA_M32R2:
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c->isa_level |= MIPS_CPU_ISA_M32R2;
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case MIPS_CPU_ISA_M32R1:
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c->isa_level |= MIPS_CPU_ISA_M32R1;
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case MIPS_CPU_ISA_II:
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c->isa_level |= MIPS_CPU_ISA_II;
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break;
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}
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}
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static char unknown_isa[] = KERN_ERR \
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"Unsupported ISA type, c0.config0: %d.";
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static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
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{
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unsigned int config6;
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/* It's implementation dependent how the FTLB can be enabled */
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switch (c->cputype) {
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case CPU_PROAPTIV:
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case CPU_P5600:
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/* proAptiv & related cores use Config6 to enable the FTLB */
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config6 = read_c0_config6();
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if (enable)
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/* Enable FTLB */
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write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
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else
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/* Disable FTLB */
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write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
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back_to_back_c0_hazard();
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break;
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}
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}
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static inline unsigned int decode_config0(struct cpuinfo_mips *c)
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{
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unsigned int config0;
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int isa;
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config0 = read_c0_config();
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/*
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* Look for Standard TLB or Dual VTLB and FTLB
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*/
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if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
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(((config0 & MIPS_CONF_MT) >> 7) == 4))
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c->options |= MIPS_CPU_TLB;
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isa = (config0 & MIPS_CONF_AT) >> 13;
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switch (isa) {
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case 0:
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switch ((config0 & MIPS_CONF_AR) >> 10) {
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case 0:
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set_isa(c, MIPS_CPU_ISA_M32R1);
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break;
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case 1:
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set_isa(c, MIPS_CPU_ISA_M32R2);
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break;
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default:
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goto unknown;
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}
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break;
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case 2:
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switch ((config0 & MIPS_CONF_AR) >> 10) {
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case 0:
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set_isa(c, MIPS_CPU_ISA_M64R1);
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break;
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case 1:
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set_isa(c, MIPS_CPU_ISA_M64R2);
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break;
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default:
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goto unknown;
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}
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break;
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default:
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goto unknown;
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}
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return config0 & MIPS_CONF_M;
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unknown:
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panic(unknown_isa, config0);
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}
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static inline unsigned int decode_config1(struct cpuinfo_mips *c)
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{
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unsigned int config1;
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config1 = read_c0_config1();
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if (config1 & MIPS_CONF1_MD)
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c->ases |= MIPS_ASE_MDMX;
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if (config1 & MIPS_CONF1_WR)
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c->options |= MIPS_CPU_WATCH;
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if (config1 & MIPS_CONF1_CA)
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c->ases |= MIPS_ASE_MIPS16;
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if (config1 & MIPS_CONF1_EP)
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c->options |= MIPS_CPU_EJTAG;
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if (config1 & MIPS_CONF1_FP) {
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c->options |= MIPS_CPU_FPU;
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c->options |= MIPS_CPU_32FPR;
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}
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if (cpu_has_tlb) {
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c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
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c->tlbsizevtlb = c->tlbsize;
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c->tlbsizeftlbsets = 0;
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}
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return config1 & MIPS_CONF_M;
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}
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static inline unsigned int decode_config2(struct cpuinfo_mips *c)
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{
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unsigned int config2;
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config2 = read_c0_config2();
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if (config2 & MIPS_CONF2_SL)
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c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
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return config2 & MIPS_CONF_M;
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}
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static inline unsigned int decode_config3(struct cpuinfo_mips *c)
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{
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unsigned int config3;
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config3 = read_c0_config3();
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if (config3 & MIPS_CONF3_SM) {
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c->ases |= MIPS_ASE_SMARTMIPS;
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c->options |= MIPS_CPU_RIXI;
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}
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if (config3 & MIPS_CONF3_RXI)
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c->options |= MIPS_CPU_RIXI;
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if (config3 & MIPS_CONF3_DSP)
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c->ases |= MIPS_ASE_DSP;
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if (config3 & MIPS_CONF3_DSP2P)
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c->ases |= MIPS_ASE_DSP2P;
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if (config3 & MIPS_CONF3_VINT)
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c->options |= MIPS_CPU_VINT;
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if (config3 & MIPS_CONF3_VEIC)
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c->options |= MIPS_CPU_VEIC;
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if (config3 & MIPS_CONF3_MT)
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c->ases |= MIPS_ASE_MIPSMT;
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if (config3 & MIPS_CONF3_ULRI)
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c->options |= MIPS_CPU_ULRI;
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if (config3 & MIPS_CONF3_ISA)
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c->options |= MIPS_CPU_MICROMIPS;
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if (config3 & MIPS_CONF3_VZ)
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c->ases |= MIPS_ASE_VZ;
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if (config3 & MIPS_CONF3_SC)
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c->options |= MIPS_CPU_SEGMENTS;
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if (config3 & MIPS_CONF3_MSA)
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c->ases |= MIPS_ASE_MSA;
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/* Only tested on 32-bit cores */
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if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT))
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c->options |= MIPS_CPU_HTW;
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return config3 & MIPS_CONF_M;
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}
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static inline unsigned int decode_config4(struct cpuinfo_mips *c)
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{
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unsigned int config4;
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unsigned int newcf4;
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unsigned int mmuextdef;
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unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
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config4 = read_c0_config4();
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if (cpu_has_tlb) {
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if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
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c->options |= MIPS_CPU_TLBINV;
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mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
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switch (mmuextdef) {
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case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
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c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
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c->tlbsizevtlb = c->tlbsize;
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break;
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case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
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c->tlbsizevtlb +=
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((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
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MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
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c->tlbsize = c->tlbsizevtlb;
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ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
|
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/* fall through */
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case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
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if (mips_ftlb_disabled)
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break;
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newcf4 = (config4 & ~ftlb_page) |
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(page_size_ftlb(mmuextdef) <<
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MIPS_CONF4_FTLBPAGESIZE_SHIFT);
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write_c0_config4(newcf4);
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back_to_back_c0_hazard();
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config4 = read_c0_config4();
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if (config4 != newcf4) {
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pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
|
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PAGE_SIZE, config4);
|
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/* Switch FTLB off */
|
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set_ftlb_enable(c, 0);
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break;
|
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}
|
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c->tlbsizeftlbsets = 1 <<
|
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((config4 & MIPS_CONF4_FTLBSETS) >>
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MIPS_CONF4_FTLBSETS_SHIFT);
|
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c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
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MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
|
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c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
|
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mips_has_ftlb_configured = 1;
|
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break;
|
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}
|
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}
|
|
|
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c->kscratch_mask = (config4 >> 16) & 0xff;
|
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|
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return config4 & MIPS_CONF_M;
|
|
}
|
|
|
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static inline unsigned int decode_config5(struct cpuinfo_mips *c)
|
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{
|
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unsigned int config5;
|
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|
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config5 = read_c0_config5();
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config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
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write_c0_config5(config5);
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|
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if (config5 & MIPS_CONF5_EVA)
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c->options |= MIPS_CPU_EVA;
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if (config5 & MIPS_CONF5_MRP)
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c->options |= MIPS_CPU_MAAR;
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return config5 & MIPS_CONF_M;
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}
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|
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static void decode_configs(struct cpuinfo_mips *c)
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{
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int ok;
|
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|
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/* MIPS32 or MIPS64 compliant CPU. */
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c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
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MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
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c->scache.flags = MIPS_CACHE_NOT_PRESENT;
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|
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/* Enable FTLB if present and not disabled */
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set_ftlb_enable(c, !mips_ftlb_disabled);
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|
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ok = decode_config0(c); /* Read Config registers. */
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BUG_ON(!ok); /* Arch spec violation! */
|
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if (ok)
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ok = decode_config1(c);
|
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if (ok)
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ok = decode_config2(c);
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if (ok)
|
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ok = decode_config3(c);
|
|
if (ok)
|
|
ok = decode_config4(c);
|
|
if (ok)
|
|
ok = decode_config5(c);
|
|
|
|
mips_probe_watch_registers(c);
|
|
|
|
if (cpu_has_rixi) {
|
|
/* Enable the RIXI exceptions */
|
|
write_c0_pagegrain(read_c0_pagegrain() | PG_IEC);
|
|
back_to_back_c0_hazard();
|
|
/* Verify the IEC bit is set */
|
|
if (read_c0_pagegrain() & PG_IEC)
|
|
c->options |= MIPS_CPU_RIXIEX;
|
|
}
|
|
|
|
#ifndef CONFIG_MIPS_CPS
|
|
if (cpu_has_mips_r2) {
|
|
c->core = get_ebase_cpunum();
|
|
if (cpu_has_mipsmt)
|
|
c->core >>= fls(core_nvpes()) - 1;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
|
|
| MIPS_CPU_COUNTER)
|
|
|
|
static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|
{
|
|
switch (c->processor_id & PRID_IMP_MASK) {
|
|
case PRID_IMP_R2000:
|
|
c->cputype = CPU_R2000;
|
|
__cpu_name[cpu] = "R2000";
|
|
c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
|
|
MIPS_CPU_NOFPUEX;
|
|
if (__cpu_has_fpu())
|
|
c->options |= MIPS_CPU_FPU;
|
|
c->tlbsize = 64;
|
|
break;
|
|
case PRID_IMP_R3000:
|
|
if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
|
|
if (cpu_has_confreg()) {
|
|
c->cputype = CPU_R3081E;
|
|
__cpu_name[cpu] = "R3081";
|
|
} else {
|
|
c->cputype = CPU_R3000A;
|
|
__cpu_name[cpu] = "R3000A";
|
|
}
|
|
} else {
|
|
c->cputype = CPU_R3000;
|
|
__cpu_name[cpu] = "R3000";
|
|
}
|
|
c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
|
|
MIPS_CPU_NOFPUEX;
|
|
if (__cpu_has_fpu())
|
|
c->options |= MIPS_CPU_FPU;
|
|
c->tlbsize = 64;
|
|
break;
|
|
case PRID_IMP_R4000:
|
|
if (read_c0_config() & CONF_SC) {
|
|
if ((c->processor_id & PRID_REV_MASK) >=
|
|
PRID_REV_R4400) {
|
|
c->cputype = CPU_R4400PC;
|
|
__cpu_name[cpu] = "R4400PC";
|
|
} else {
|
|
c->cputype = CPU_R4000PC;
|
|
__cpu_name[cpu] = "R4000PC";
|
|
}
|
|
} else {
|
|
int cca = read_c0_config() & CONF_CM_CMASK;
|
|
int mc;
|
|
|
|
/*
|
|
* SC and MC versions can't be reliably told apart,
|
|
* but only the latter support coherent caching
|
|
* modes so assume the firmware has set the KSEG0
|
|
* coherency attribute reasonably (if uncached, we
|
|
* assume SC).
|
|
*/
|
|
switch (cca) {
|
|
case CONF_CM_CACHABLE_CE:
|
|
case CONF_CM_CACHABLE_COW:
|
|
case CONF_CM_CACHABLE_CUW:
|
|
mc = 1;
|
|
break;
|
|
default:
|
|
mc = 0;
|
|
break;
|
|
}
|
|
if ((c->processor_id & PRID_REV_MASK) >=
|
|
PRID_REV_R4400) {
|
|
c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
|
|
__cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
|
|
} else {
|
|
c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
|
|
__cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
|
|
}
|
|
}
|
|
|
|
set_isa(c, MIPS_CPU_ISA_III);
|
|
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_WATCH | MIPS_CPU_VCE |
|
|
MIPS_CPU_LLSC;
|
|
c->tlbsize = 48;
|
|
break;
|
|
case PRID_IMP_VR41XX:
|
|
set_isa(c, MIPS_CPU_ISA_III);
|
|
c->options = R4K_OPTS;
|
|
c->tlbsize = 32;
|
|
switch (c->processor_id & 0xf0) {
|
|
case PRID_REV_VR4111:
|
|
c->cputype = CPU_VR4111;
|
|
__cpu_name[cpu] = "NEC VR4111";
|
|
break;
|
|
case PRID_REV_VR4121:
|
|
c->cputype = CPU_VR4121;
|
|
__cpu_name[cpu] = "NEC VR4121";
|
|
break;
|
|
case PRID_REV_VR4122:
|
|
if ((c->processor_id & 0xf) < 0x3) {
|
|
c->cputype = CPU_VR4122;
|
|
__cpu_name[cpu] = "NEC VR4122";
|
|
} else {
|
|
c->cputype = CPU_VR4181A;
|
|
__cpu_name[cpu] = "NEC VR4181A";
|
|
}
|
|
break;
|
|
case PRID_REV_VR4130:
|
|
if ((c->processor_id & 0xf) < 0x4) {
|
|
c->cputype = CPU_VR4131;
|
|
__cpu_name[cpu] = "NEC VR4131";
|
|
} else {
|
|
c->cputype = CPU_VR4133;
|
|
c->options |= MIPS_CPU_LLSC;
|
|
__cpu_name[cpu] = "NEC VR4133";
|
|
}
|
|
break;
|
|
default:
|
|
printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
|
|
c->cputype = CPU_VR41XX;
|
|
__cpu_name[cpu] = "NEC Vr41xx";
|
|
break;
|
|
}
|
|
break;
|
|
case PRID_IMP_R4300:
|
|
c->cputype = CPU_R4300;
|
|
__cpu_name[cpu] = "R4300";
|
|
set_isa(c, MIPS_CPU_ISA_III);
|
|
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_LLSC;
|
|
c->tlbsize = 32;
|
|
break;
|
|
case PRID_IMP_R4600:
|
|
c->cputype = CPU_R4600;
|
|
__cpu_name[cpu] = "R4600";
|
|
set_isa(c, MIPS_CPU_ISA_III);
|
|
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_LLSC;
|
|
c->tlbsize = 48;
|
|
break;
|
|
#if 0
|
|
case PRID_IMP_R4650:
|
|
/*
|
|
* This processor doesn't have an MMU, so it's not
|
|
* "real easy" to run Linux on it. It is left purely
|
|
* for documentation. Commented out because it shares
|
|
* it's c0_prid id number with the TX3900.
|
|
*/
|
|
c->cputype = CPU_R4650;
|
|
__cpu_name[cpu] = "R4650";
|
|
set_isa(c, MIPS_CPU_ISA_III);
|
|
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
|
|
c->tlbsize = 48;
|
|
break;
|
|
#endif
|
|
case PRID_IMP_TX39:
|
|
c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
|
|
|
|
if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
|
|
c->cputype = CPU_TX3927;
|
|
__cpu_name[cpu] = "TX3927";
|
|
c->tlbsize = 64;
|
|
} else {
|
|
switch (c->processor_id & PRID_REV_MASK) {
|
|
case PRID_REV_TX3912:
|
|
c->cputype = CPU_TX3912;
|
|
__cpu_name[cpu] = "TX3912";
|
|
c->tlbsize = 32;
|
|
break;
|
|
case PRID_REV_TX3922:
|
|
c->cputype = CPU_TX3922;
|
|
__cpu_name[cpu] = "TX3922";
|
|
c->tlbsize = 64;
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
case PRID_IMP_R4700:
|
|
c->cputype = CPU_R4700;
|
|
__cpu_name[cpu] = "R4700";
|
|
set_isa(c, MIPS_CPU_ISA_III);
|
|
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_LLSC;
|
|
c->tlbsize = 48;
|
|
break;
|
|
case PRID_IMP_TX49:
|
|
c->cputype = CPU_TX49XX;
|
|
__cpu_name[cpu] = "R49XX";
|
|
set_isa(c, MIPS_CPU_ISA_III);
|
|
c->options = R4K_OPTS | MIPS_CPU_LLSC;
|
|
if (!(c->processor_id & 0x08))
|
|
c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
|
|
c->tlbsize = 48;
|
|
break;
|
|
case PRID_IMP_R5000:
|
|
c->cputype = CPU_R5000;
|
|
__cpu_name[cpu] = "R5000";
|
|
set_isa(c, MIPS_CPU_ISA_IV);
|
|
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_LLSC;
|
|
c->tlbsize = 48;
|
|
break;
|
|
case PRID_IMP_R5432:
|
|
c->cputype = CPU_R5432;
|
|
__cpu_name[cpu] = "R5432";
|
|
set_isa(c, MIPS_CPU_ISA_IV);
|
|
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_WATCH | MIPS_CPU_LLSC;
|
|
c->tlbsize = 48;
|
|
break;
|
|
case PRID_IMP_R5500:
|
|
c->cputype = CPU_R5500;
|
|
__cpu_name[cpu] = "R5500";
|
|
set_isa(c, MIPS_CPU_ISA_IV);
|
|
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_WATCH | MIPS_CPU_LLSC;
|
|
c->tlbsize = 48;
|
|
break;
|
|
case PRID_IMP_NEVADA:
|
|
c->cputype = CPU_NEVADA;
|
|
__cpu_name[cpu] = "Nevada";
|
|
set_isa(c, MIPS_CPU_ISA_IV);
|
|
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
|
|
c->tlbsize = 48;
|
|
break;
|
|
case PRID_IMP_R6000:
|
|
c->cputype = CPU_R6000;
|
|
__cpu_name[cpu] = "R6000";
|
|
set_isa(c, MIPS_CPU_ISA_II);
|
|
c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
|
|
MIPS_CPU_LLSC;
|
|
c->tlbsize = 32;
|
|
break;
|
|
case PRID_IMP_R6000A:
|
|
c->cputype = CPU_R6000A;
|
|
__cpu_name[cpu] = "R6000A";
|
|
set_isa(c, MIPS_CPU_ISA_II);
|
|
c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
|
|
MIPS_CPU_LLSC;
|
|
c->tlbsize = 32;
|
|
break;
|
|
case PRID_IMP_RM7000:
|
|
c->cputype = CPU_RM7000;
|
|
__cpu_name[cpu] = "RM7000";
|
|
set_isa(c, MIPS_CPU_ISA_IV);
|
|
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_LLSC;
|
|
/*
|
|
* Undocumented RM7000: Bit 29 in the info register of
|
|
* the RM7000 v2.0 indicates if the TLB has 48 or 64
|
|
* entries.
|
|
*
|
|
* 29 1 => 64 entry JTLB
|
|
* 0 => 48 entry JTLB
|
|
*/
|
|
c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
|
|
break;
|
|
case PRID_IMP_R8000:
|
|
c->cputype = CPU_R8000;
|
|
__cpu_name[cpu] = "RM8000";
|
|
set_isa(c, MIPS_CPU_ISA_IV);
|
|
c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
|
|
MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_LLSC;
|
|
c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
|
|
break;
|
|
case PRID_IMP_R10000:
|
|
c->cputype = CPU_R10000;
|
|
__cpu_name[cpu] = "R10000";
|
|
set_isa(c, MIPS_CPU_ISA_IV);
|
|
c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
|
|
MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
|
|
MIPS_CPU_LLSC;
|
|
c->tlbsize = 64;
|
|
break;
|
|
case PRID_IMP_R12000:
|
|
c->cputype = CPU_R12000;
|
|
__cpu_name[cpu] = "R12000";
|
|
set_isa(c, MIPS_CPU_ISA_IV);
|
|
c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
|
|
MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
|
|
MIPS_CPU_LLSC;
|
|
c->tlbsize = 64;
|
|
break;
|
|
case PRID_IMP_R14000:
|
|
c->cputype = CPU_R14000;
|
|
__cpu_name[cpu] = "R14000";
|
|
set_isa(c, MIPS_CPU_ISA_IV);
|
|
c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
|
|
MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
|
|
MIPS_CPU_LLSC;
|
|
c->tlbsize = 64;
|
|
break;
|
|
case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
|
|
switch (c->processor_id & PRID_REV_MASK) {
|
|
case PRID_REV_LOONGSON2E:
|
|
c->cputype = CPU_LOONGSON2;
|
|
__cpu_name[cpu] = "ICT Loongson-2";
|
|
set_elf_platform(cpu, "loongson2e");
|
|
set_isa(c, MIPS_CPU_ISA_III);
|
|
break;
|
|
case PRID_REV_LOONGSON2F:
|
|
c->cputype = CPU_LOONGSON2;
|
|
__cpu_name[cpu] = "ICT Loongson-2";
|
|
set_elf_platform(cpu, "loongson2f");
|
|
set_isa(c, MIPS_CPU_ISA_III);
|
|
break;
|
|
case PRID_REV_LOONGSON3A:
|
|
c->cputype = CPU_LOONGSON3;
|
|
__cpu_name[cpu] = "ICT Loongson-3";
|
|
set_elf_platform(cpu, "loongson3a");
|
|
set_isa(c, MIPS_CPU_ISA_M64R1);
|
|
break;
|
|
case PRID_REV_LOONGSON3B_R1:
|
|
case PRID_REV_LOONGSON3B_R2:
|
|
c->cputype = CPU_LOONGSON3;
|
|
__cpu_name[cpu] = "ICT Loongson-3";
|
|
set_elf_platform(cpu, "loongson3b");
|
|
set_isa(c, MIPS_CPU_ISA_M64R1);
|
|
break;
|
|
}
|
|
|
|
c->options = R4K_OPTS |
|
|
MIPS_CPU_FPU | MIPS_CPU_LLSC |
|
|
MIPS_CPU_32FPR;
|
|
c->tlbsize = 64;
|
|
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
|
|
break;
|
|
case PRID_IMP_LOONGSON_32: /* Loongson-1 */
|
|
decode_configs(c);
|
|
|
|
c->cputype = CPU_LOONGSON1;
|
|
|
|
switch (c->processor_id & PRID_REV_MASK) {
|
|
case PRID_REV_LOONGSON1B:
|
|
__cpu_name[cpu] = "Loongson 1B";
|
|
break;
|
|
}
|
|
|
|
break;
|
|
}
|
|
}
|
|
|
|
static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
|
|
{
|
|
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
|
|
switch (c->processor_id & PRID_IMP_MASK) {
|
|
case PRID_IMP_4KC:
|
|
c->cputype = CPU_4KC;
|
|
c->writecombine = _CACHE_UNCACHED;
|
|
__cpu_name[cpu] = "MIPS 4Kc";
|
|
break;
|
|
case PRID_IMP_4KEC:
|
|
case PRID_IMP_4KECR2:
|
|
c->cputype = CPU_4KEC;
|
|
c->writecombine = _CACHE_UNCACHED;
|
|
__cpu_name[cpu] = "MIPS 4KEc";
|
|
break;
|
|
case PRID_IMP_4KSC:
|
|
case PRID_IMP_4KSD:
|
|
c->cputype = CPU_4KSC;
|
|
c->writecombine = _CACHE_UNCACHED;
|
|
__cpu_name[cpu] = "MIPS 4KSc";
|
|
break;
|
|
case PRID_IMP_5KC:
|
|
c->cputype = CPU_5KC;
|
|
c->writecombine = _CACHE_UNCACHED;
|
|
__cpu_name[cpu] = "MIPS 5Kc";
|
|
break;
|
|
case PRID_IMP_5KE:
|
|
c->cputype = CPU_5KE;
|
|
c->writecombine = _CACHE_UNCACHED;
|
|
__cpu_name[cpu] = "MIPS 5KE";
|
|
break;
|
|
case PRID_IMP_20KC:
|
|
c->cputype = CPU_20KC;
|
|
c->writecombine = _CACHE_UNCACHED;
|
|
__cpu_name[cpu] = "MIPS 20Kc";
|
|
break;
|
|
case PRID_IMP_24K:
|
|
c->cputype = CPU_24K;
|
|
c->writecombine = _CACHE_UNCACHED;
|
|
__cpu_name[cpu] = "MIPS 24Kc";
|
|
break;
|
|
case PRID_IMP_24KE:
|
|
c->cputype = CPU_24K;
|
|
c->writecombine = _CACHE_UNCACHED;
|
|
__cpu_name[cpu] = "MIPS 24KEc";
|
|
break;
|
|
case PRID_IMP_25KF:
|
|
c->cputype = CPU_25KF;
|
|
c->writecombine = _CACHE_UNCACHED;
|
|
__cpu_name[cpu] = "MIPS 25Kc";
|
|
break;
|
|
case PRID_IMP_34K:
|
|
c->cputype = CPU_34K;
|
|
c->writecombine = _CACHE_UNCACHED;
|
|
__cpu_name[cpu] = "MIPS 34Kc";
|
|
break;
|
|
case PRID_IMP_74K:
|
|
c->cputype = CPU_74K;
|
|
c->writecombine = _CACHE_UNCACHED;
|
|
__cpu_name[cpu] = "MIPS 74Kc";
|
|
break;
|
|
case PRID_IMP_M14KC:
|
|
c->cputype = CPU_M14KC;
|
|
c->writecombine = _CACHE_UNCACHED;
|
|
__cpu_name[cpu] = "MIPS M14Kc";
|
|
break;
|
|
case PRID_IMP_M14KEC:
|
|
c->cputype = CPU_M14KEC;
|
|
c->writecombine = _CACHE_UNCACHED;
|
|
__cpu_name[cpu] = "MIPS M14KEc";
|
|
break;
|
|
case PRID_IMP_1004K:
|
|
c->cputype = CPU_1004K;
|
|
c->writecombine = _CACHE_UNCACHED;
|
|
__cpu_name[cpu] = "MIPS 1004Kc";
|
|
break;
|
|
case PRID_IMP_1074K:
|
|
c->cputype = CPU_1074K;
|
|
c->writecombine = _CACHE_UNCACHED;
|
|
__cpu_name[cpu] = "MIPS 1074Kc";
|
|
break;
|
|
case PRID_IMP_INTERAPTIV_UP:
|
|
c->cputype = CPU_INTERAPTIV;
|
|
__cpu_name[cpu] = "MIPS interAptiv";
|
|
break;
|
|
case PRID_IMP_INTERAPTIV_MP:
|
|
c->cputype = CPU_INTERAPTIV;
|
|
__cpu_name[cpu] = "MIPS interAptiv (multi)";
|
|
break;
|
|
case PRID_IMP_PROAPTIV_UP:
|
|
c->cputype = CPU_PROAPTIV;
|
|
__cpu_name[cpu] = "MIPS proAptiv";
|
|
break;
|
|
case PRID_IMP_PROAPTIV_MP:
|
|
c->cputype = CPU_PROAPTIV;
|
|
__cpu_name[cpu] = "MIPS proAptiv (multi)";
|
|
break;
|
|
case PRID_IMP_P5600:
|
|
c->cputype = CPU_P5600;
|
|
__cpu_name[cpu] = "MIPS P5600";
|
|
break;
|
|
case PRID_IMP_M5150:
|
|
c->cputype = CPU_M5150;
|
|
__cpu_name[cpu] = "MIPS M5150";
|
|
break;
|
|
}
|
|
|
|
decode_configs(c);
|
|
|
|
spram_config();
|
|
}
|
|
|
|
static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
|
|
{
|
|
decode_configs(c);
|
|
switch (c->processor_id & PRID_IMP_MASK) {
|
|
case PRID_IMP_AU1_REV1:
|
|
case PRID_IMP_AU1_REV2:
|
|
c->cputype = CPU_ALCHEMY;
|
|
switch ((c->processor_id >> 24) & 0xff) {
|
|
case 0:
|
|
__cpu_name[cpu] = "Au1000";
|
|
break;
|
|
case 1:
|
|
__cpu_name[cpu] = "Au1500";
|
|
break;
|
|
case 2:
|
|
__cpu_name[cpu] = "Au1100";
|
|
break;
|
|
case 3:
|
|
__cpu_name[cpu] = "Au1550";
|
|
break;
|
|
case 4:
|
|
__cpu_name[cpu] = "Au1200";
|
|
if ((c->processor_id & PRID_REV_MASK) == 2)
|
|
__cpu_name[cpu] = "Au1250";
|
|
break;
|
|
case 5:
|
|
__cpu_name[cpu] = "Au1210";
|
|
break;
|
|
default:
|
|
__cpu_name[cpu] = "Au1xxx";
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
|
|
{
|
|
decode_configs(c);
|
|
|
|
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
|
|
switch (c->processor_id & PRID_IMP_MASK) {
|
|
case PRID_IMP_SB1:
|
|
c->cputype = CPU_SB1;
|
|
__cpu_name[cpu] = "SiByte SB1";
|
|
/* FPU in pass1 is known to have issues. */
|
|
if ((c->processor_id & PRID_REV_MASK) < 0x02)
|
|
c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
|
|
break;
|
|
case PRID_IMP_SB1A:
|
|
c->cputype = CPU_SB1A;
|
|
__cpu_name[cpu] = "SiByte SB1A";
|
|
break;
|
|
}
|
|
}
|
|
|
|
static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
|
|
{
|
|
decode_configs(c);
|
|
switch (c->processor_id & PRID_IMP_MASK) {
|
|
case PRID_IMP_SR71000:
|
|
c->cputype = CPU_SR71000;
|
|
__cpu_name[cpu] = "Sandcraft SR71000";
|
|
c->scache.ways = 8;
|
|
c->tlbsize = 64;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
|
|
{
|
|
decode_configs(c);
|
|
switch (c->processor_id & PRID_IMP_MASK) {
|
|
case PRID_IMP_PR4450:
|
|
c->cputype = CPU_PR4450;
|
|
__cpu_name[cpu] = "Philips PR4450";
|
|
set_isa(c, MIPS_CPU_ISA_M32R1);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
|
|
{
|
|
decode_configs(c);
|
|
switch (c->processor_id & PRID_IMP_MASK) {
|
|
case PRID_IMP_BMIPS32_REV4:
|
|
case PRID_IMP_BMIPS32_REV8:
|
|
c->cputype = CPU_BMIPS32;
|
|
__cpu_name[cpu] = "Broadcom BMIPS32";
|
|
set_elf_platform(cpu, "bmips32");
|
|
break;
|
|
case PRID_IMP_BMIPS3300:
|
|
case PRID_IMP_BMIPS3300_ALT:
|
|
case PRID_IMP_BMIPS3300_BUG:
|
|
c->cputype = CPU_BMIPS3300;
|
|
__cpu_name[cpu] = "Broadcom BMIPS3300";
|
|
set_elf_platform(cpu, "bmips3300");
|
|
break;
|
|
case PRID_IMP_BMIPS43XX: {
|
|
int rev = c->processor_id & PRID_REV_MASK;
|
|
|
|
if (rev >= PRID_REV_BMIPS4380_LO &&
|
|
rev <= PRID_REV_BMIPS4380_HI) {
|
|
c->cputype = CPU_BMIPS4380;
|
|
__cpu_name[cpu] = "Broadcom BMIPS4380";
|
|
set_elf_platform(cpu, "bmips4380");
|
|
} else {
|
|
c->cputype = CPU_BMIPS4350;
|
|
__cpu_name[cpu] = "Broadcom BMIPS4350";
|
|
set_elf_platform(cpu, "bmips4350");
|
|
}
|
|
break;
|
|
}
|
|
case PRID_IMP_BMIPS5000:
|
|
c->cputype = CPU_BMIPS5000;
|
|
__cpu_name[cpu] = "Broadcom BMIPS5000";
|
|
set_elf_platform(cpu, "bmips5000");
|
|
c->options |= MIPS_CPU_ULRI;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
|
|
{
|
|
decode_configs(c);
|
|
switch (c->processor_id & PRID_IMP_MASK) {
|
|
case PRID_IMP_CAVIUM_CN38XX:
|
|
case PRID_IMP_CAVIUM_CN31XX:
|
|
case PRID_IMP_CAVIUM_CN30XX:
|
|
c->cputype = CPU_CAVIUM_OCTEON;
|
|
__cpu_name[cpu] = "Cavium Octeon";
|
|
goto platform;
|
|
case PRID_IMP_CAVIUM_CN58XX:
|
|
case PRID_IMP_CAVIUM_CN56XX:
|
|
case PRID_IMP_CAVIUM_CN50XX:
|
|
case PRID_IMP_CAVIUM_CN52XX:
|
|
c->cputype = CPU_CAVIUM_OCTEON_PLUS;
|
|
__cpu_name[cpu] = "Cavium Octeon+";
|
|
platform:
|
|
set_elf_platform(cpu, "octeon");
|
|
break;
|
|
case PRID_IMP_CAVIUM_CN61XX:
|
|
case PRID_IMP_CAVIUM_CN63XX:
|
|
case PRID_IMP_CAVIUM_CN66XX:
|
|
case PRID_IMP_CAVIUM_CN68XX:
|
|
case PRID_IMP_CAVIUM_CNF71XX:
|
|
c->cputype = CPU_CAVIUM_OCTEON2;
|
|
__cpu_name[cpu] = "Cavium Octeon II";
|
|
set_elf_platform(cpu, "octeon2");
|
|
break;
|
|
case PRID_IMP_CAVIUM_CN70XX:
|
|
case PRID_IMP_CAVIUM_CN78XX:
|
|
c->cputype = CPU_CAVIUM_OCTEON3;
|
|
__cpu_name[cpu] = "Cavium Octeon III";
|
|
set_elf_platform(cpu, "octeon3");
|
|
break;
|
|
default:
|
|
printk(KERN_INFO "Unknown Octeon chip!\n");
|
|
c->cputype = CPU_UNKNOWN;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
|
|
{
|
|
decode_configs(c);
|
|
/* JZRISC does not implement the CP0 counter. */
|
|
c->options &= ~MIPS_CPU_COUNTER;
|
|
BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
|
|
switch (c->processor_id & PRID_IMP_MASK) {
|
|
case PRID_IMP_JZRISC:
|
|
c->cputype = CPU_JZRISC;
|
|
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
|
|
__cpu_name[cpu] = "Ingenic JZRISC";
|
|
break;
|
|
default:
|
|
panic("Unknown Ingenic Processor ID!");
|
|
break;
|
|
}
|
|
}
|
|
|
|
static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
|
|
{
|
|
decode_configs(c);
|
|
|
|
if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
|
|
c->cputype = CPU_ALCHEMY;
|
|
__cpu_name[cpu] = "Au1300";
|
|
/* following stuff is not for Alchemy */
|
|
return;
|
|
}
|
|
|
|
c->options = (MIPS_CPU_TLB |
|
|
MIPS_CPU_4KEX |
|
|
MIPS_CPU_COUNTER |
|
|
MIPS_CPU_DIVEC |
|
|
MIPS_CPU_WATCH |
|
|
MIPS_CPU_EJTAG |
|
|
MIPS_CPU_LLSC);
|
|
|
|
switch (c->processor_id & PRID_IMP_MASK) {
|
|
case PRID_IMP_NETLOGIC_XLP2XX:
|
|
case PRID_IMP_NETLOGIC_XLP9XX:
|
|
case PRID_IMP_NETLOGIC_XLP5XX:
|
|
c->cputype = CPU_XLP;
|
|
__cpu_name[cpu] = "Broadcom XLPII";
|
|
break;
|
|
|
|
case PRID_IMP_NETLOGIC_XLP8XX:
|
|
case PRID_IMP_NETLOGIC_XLP3XX:
|
|
c->cputype = CPU_XLP;
|
|
__cpu_name[cpu] = "Netlogic XLP";
|
|
break;
|
|
|
|
case PRID_IMP_NETLOGIC_XLR732:
|
|
case PRID_IMP_NETLOGIC_XLR716:
|
|
case PRID_IMP_NETLOGIC_XLR532:
|
|
case PRID_IMP_NETLOGIC_XLR308:
|
|
case PRID_IMP_NETLOGIC_XLR532C:
|
|
case PRID_IMP_NETLOGIC_XLR516C:
|
|
case PRID_IMP_NETLOGIC_XLR508C:
|
|
case PRID_IMP_NETLOGIC_XLR308C:
|
|
c->cputype = CPU_XLR;
|
|
__cpu_name[cpu] = "Netlogic XLR";
|
|
break;
|
|
|
|
case PRID_IMP_NETLOGIC_XLS608:
|
|
case PRID_IMP_NETLOGIC_XLS408:
|
|
case PRID_IMP_NETLOGIC_XLS404:
|
|
case PRID_IMP_NETLOGIC_XLS208:
|
|
case PRID_IMP_NETLOGIC_XLS204:
|
|
case PRID_IMP_NETLOGIC_XLS108:
|
|
case PRID_IMP_NETLOGIC_XLS104:
|
|
case PRID_IMP_NETLOGIC_XLS616B:
|
|
case PRID_IMP_NETLOGIC_XLS608B:
|
|
case PRID_IMP_NETLOGIC_XLS416B:
|
|
case PRID_IMP_NETLOGIC_XLS412B:
|
|
case PRID_IMP_NETLOGIC_XLS408B:
|
|
case PRID_IMP_NETLOGIC_XLS404B:
|
|
c->cputype = CPU_XLR;
|
|
__cpu_name[cpu] = "Netlogic XLS";
|
|
break;
|
|
|
|
default:
|
|
pr_info("Unknown Netlogic chip id [%02x]!\n",
|
|
c->processor_id);
|
|
c->cputype = CPU_XLR;
|
|
break;
|
|
}
|
|
|
|
if (c->cputype == CPU_XLP) {
|
|
set_isa(c, MIPS_CPU_ISA_M64R2);
|
|
c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
|
|
/* This will be updated again after all threads are woken up */
|
|
c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
|
|
} else {
|
|
set_isa(c, MIPS_CPU_ISA_M64R1);
|
|
c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
|
|
}
|
|
c->kscratch_mask = 0xf;
|
|
}
|
|
|
|
#ifdef CONFIG_64BIT
|
|
/* For use by uaccess.h */
|
|
u64 __ua_limit;
|
|
EXPORT_SYMBOL(__ua_limit);
|
|
#endif
|
|
|
|
const char *__cpu_name[NR_CPUS];
|
|
const char *__elf_platform;
|
|
|
|
void cpu_probe(void)
|
|
{
|
|
struct cpuinfo_mips *c = ¤t_cpu_data;
|
|
unsigned int cpu = smp_processor_id();
|
|
|
|
c->processor_id = PRID_IMP_UNKNOWN;
|
|
c->fpu_id = FPIR_IMP_NONE;
|
|
c->cputype = CPU_UNKNOWN;
|
|
c->writecombine = _CACHE_UNCACHED;
|
|
|
|
c->processor_id = read_c0_prid();
|
|
switch (c->processor_id & PRID_COMP_MASK) {
|
|
case PRID_COMP_LEGACY:
|
|
cpu_probe_legacy(c, cpu);
|
|
break;
|
|
case PRID_COMP_MIPS:
|
|
cpu_probe_mips(c, cpu);
|
|
break;
|
|
case PRID_COMP_ALCHEMY:
|
|
cpu_probe_alchemy(c, cpu);
|
|
break;
|
|
case PRID_COMP_SIBYTE:
|
|
cpu_probe_sibyte(c, cpu);
|
|
break;
|
|
case PRID_COMP_BROADCOM:
|
|
cpu_probe_broadcom(c, cpu);
|
|
break;
|
|
case PRID_COMP_SANDCRAFT:
|
|
cpu_probe_sandcraft(c, cpu);
|
|
break;
|
|
case PRID_COMP_NXP:
|
|
cpu_probe_nxp(c, cpu);
|
|
break;
|
|
case PRID_COMP_CAVIUM:
|
|
cpu_probe_cavium(c, cpu);
|
|
break;
|
|
case PRID_COMP_INGENIC:
|
|
cpu_probe_ingenic(c, cpu);
|
|
break;
|
|
case PRID_COMP_NETLOGIC:
|
|
cpu_probe_netlogic(c, cpu);
|
|
break;
|
|
}
|
|
|
|
BUG_ON(!__cpu_name[cpu]);
|
|
BUG_ON(c->cputype == CPU_UNKNOWN);
|
|
|
|
/*
|
|
* Platform code can force the cpu type to optimize code
|
|
* generation. In that case be sure the cpu type is correctly
|
|
* manually setup otherwise it could trigger some nasty bugs.
|
|
*/
|
|
BUG_ON(current_cpu_type() != c->cputype);
|
|
|
|
if (mips_fpu_disabled)
|
|
c->options &= ~MIPS_CPU_FPU;
|
|
|
|
if (mips_dsp_disabled)
|
|
c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
|
|
|
|
if (mips_htw_disabled) {
|
|
c->options &= ~MIPS_CPU_HTW;
|
|
write_c0_pwctl(read_c0_pwctl() &
|
|
~(1 << MIPS_PWCTL_PWEN_SHIFT));
|
|
}
|
|
|
|
if (c->options & MIPS_CPU_FPU) {
|
|
c->fpu_id = cpu_get_fpu_id();
|
|
|
|
if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
|
|
MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
|
|
if (c->fpu_id & MIPS_FPIR_3D)
|
|
c->ases |= MIPS_ASE_MIPS3D;
|
|
if (c->fpu_id & MIPS_FPIR_FREP)
|
|
c->options |= MIPS_CPU_FRE;
|
|
}
|
|
}
|
|
|
|
if (cpu_has_mips_r2) {
|
|
c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
|
|
/* R2 has Performance Counter Interrupt indicator */
|
|
c->options |= MIPS_CPU_PCI;
|
|
}
|
|
else
|
|
c->srsets = 1;
|
|
|
|
if (cpu_has_msa) {
|
|
c->msa_id = cpu_get_msa_id();
|
|
WARN(c->msa_id & MSA_IR_WRPF,
|
|
"Vector register partitioning unimplemented!");
|
|
}
|
|
|
|
cpu_probe_vmbits(c);
|
|
|
|
#ifdef CONFIG_64BIT
|
|
if (cpu == 0)
|
|
__ua_limit = ~((1ull << cpu_vmbits) - 1);
|
|
#endif
|
|
}
|
|
|
|
void cpu_report(void)
|
|
{
|
|
struct cpuinfo_mips *c = ¤t_cpu_data;
|
|
|
|
pr_info("CPU%d revision is: %08x (%s)\n",
|
|
smp_processor_id(), c->processor_id, cpu_name_string());
|
|
if (c->options & MIPS_CPU_FPU)
|
|
printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
|
|
if (cpu_has_msa)
|
|
pr_info("MSA revision is: %08x\n", c->msa_id);
|
|
}
|