cfe4645e17
This change fixes dcn10 front end reset sequence. Previously we would reset front end during flip which led to issues in certain MPO and 4k/5k scenarios. We would also never properly power gate our front end. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
145 lines
4.1 KiB
C
145 lines
4.1 KiB
C
/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "reg_helper.h"
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#include "dcn10_mpc.h"
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#define REG(reg)\
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mpcc10->mpcc_regs->reg
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#define CTX \
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mpcc10->base.ctx
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#undef FN
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#define FN(reg_name, field_name) \
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mpcc10->mpcc_shift->field_name, mpcc10->mpcc_mask->field_name
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#define MODE_TOP_ONLY 1
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#define MODE_BLEND 3
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#define BLND_PP_ALPHA 0
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#define BLND_GLOBAL_ALPHA 2
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void dcn10_mpcc_set_bg_color(
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struct mpcc *mpcc,
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struct tg_color *bg_color)
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{
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struct dcn10_mpcc *mpcc10 = TO_DCN10_MPCC(mpcc);
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/* mpc color is 12 bit. tg_color is 10 bit */
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/* todo: might want to use 16 bit to represent color and have each
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* hw block translate to correct color depth.
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*/
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uint32_t bg_r_cr = bg_color->color_r_cr << 2;
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uint32_t bg_g_y = bg_color->color_g_y << 2;
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uint32_t bg_b_cb = bg_color->color_b_cb << 2;
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REG_SET(MPCC_BG_R_CR, 0,
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MPCC_BG_R_CR, bg_r_cr);
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REG_SET(MPCC_BG_G_Y, 0,
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MPCC_BG_G_Y, bg_g_y);
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REG_SET(MPCC_BG_B_CB, 0,
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MPCC_BG_B_CB, bg_b_cb);
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}
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static void set_output_mux(struct dcn10_mpcc *mpcc10, int opp_id, int mpcc_id)
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{
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ASSERT(mpcc10->base.opp_id == 0xf || opp_id == mpcc10->base.opp_id);
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mpcc10->base.opp_id = opp_id;
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REG_UPDATE(OPP_PIPE_CONTROL[opp_id], OPP_PIPE_CLOCK_EN, 1);
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REG_SET(MUX[opp_id], 0, MPC_OUT_MUX, mpcc_id);
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}
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static void reset_output_mux(struct dcn10_mpcc *mpcc10)
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{
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REG_SET(MUX[mpcc10->base.opp_id], 0, MPC_OUT_MUX, 0xf);
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REG_UPDATE(OPP_PIPE_CONTROL[mpcc10->base.opp_id], OPP_PIPE_CLOCK_EN, 0);
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mpcc10->base.opp_id = 0xf;
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}
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static void dcn10_mpcc_set(struct mpcc *mpcc, struct mpcc_cfg *cfg)
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{
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struct dcn10_mpcc *mpcc10 = TO_DCN10_MPCC(mpcc);
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int alpha_blnd_mode = cfg->per_pixel_alpha ?
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BLND_PP_ALPHA : BLND_GLOBAL_ALPHA;
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int mpcc_mode = cfg->bot_mpcc_id != 0xf ?
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MODE_BLEND : MODE_TOP_ONLY;
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REG_SET(MPCC_OPP_ID, 0,
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MPCC_OPP_ID, cfg->opp_id);
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REG_SET(MPCC_TOP_SEL, 0,
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MPCC_TOP_SEL, cfg->top_dpp_id);
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REG_SET(MPCC_BOT_SEL, 0,
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MPCC_BOT_SEL, cfg->bot_mpcc_id);
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REG_SET_4(MPCC_CONTROL, 0xffffffff,
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MPCC_MODE, mpcc_mode,
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MPCC_ALPHA_BLND_MODE, alpha_blnd_mode,
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MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha,
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MPCC_BLND_ACTIVE_OVERLAP_ONLY, cfg->top_of_tree);
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if (cfg->top_of_tree) {
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if (cfg->opp_id != 0xf)
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set_output_mux(mpcc10, cfg->opp_id, mpcc->inst);
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else if (mpcc->opp_id != 0xf)
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reset_output_mux(mpcc10);
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}
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mpcc10->base.opp_id = cfg->opp_id;
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}
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static void dcn10_mpcc_wait_idle(struct mpcc *mpcc)
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{
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struct dcn10_mpcc *mpcc10 = TO_DCN10_MPCC(mpcc);
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REG_WAIT(MPCC_STATUS, MPCC_BUSY, 0, 1000, 1000);
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}
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const struct mpcc_funcs dcn10_mpcc_funcs = {
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.set = dcn10_mpcc_set,
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.wait_for_idle = dcn10_mpcc_wait_idle,
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.set_bg_color = dcn10_mpcc_set_bg_color,
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};
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void dcn10_mpcc_construct(struct dcn10_mpcc *mpcc10,
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struct dc_context *ctx,
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const struct dcn_mpcc_registers *mpcc_regs,
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const struct dcn_mpcc_shift *mpcc_shift,
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const struct dcn_mpcc_mask *mpcc_mask,
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int inst)
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{
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mpcc10->base.ctx = ctx;
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mpcc10->base.inst = inst;
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mpcc10->base.funcs = &dcn10_mpcc_funcs;
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mpcc10->mpcc_regs = mpcc_regs;
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mpcc10->mpcc_shift = mpcc_shift;
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mpcc10->mpcc_mask = mpcc_mask;
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mpcc10->base.opp_id = inst;
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}
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