Chander Kashyap cdf64eeeb0 clk: exynos5420: fix cpll clock register offsets ... Fixes cpll control and lock register offset values for Exynos5420 SoC. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>		2013-12-04 10:46:45 -08:00
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clk-exynos4.c	The common clk framework changes for 3.12 are dominated by clock driver	2013-09-09 15:49:04 -07:00
clk-exynos5250.c	clk: samsung: exynos5250: Simplify registration of PLL rate tables	2013-09-06 13:34:05 -07:00
clk-exynos5420.c	clk: exynos5420: fix cpll clock register offsets	2013-12-04 10:46:45 -08:00
clk-exynos5440.c	clk: samsung: Modify _get_rate() helper to use __clk_lookup()	2013-09-06 13:33:15 -07:00
clk-exynos-audss.c	clk: add CLK_SET_RATE_NO_REPARENT flag	2013-08-19 12:27:17 -07:00
clk-pll.c	clk: samsung: pll: Add support for rate configuration of PLL46xx	2013-09-06 13:33:47 -07:00
clk-pll.h	clk: samsung: pll: Add support for rate configuration of PLL46xx	2013-09-06 13:33:47 -07:00
clk-s3c64xx.c	clk: s3c64xx: Fix incorrect placement of __initdata	2013-08-27 18:36:20 -07:00
clk.c	clk: samsung: Modify _get_rate() helper to use __clk_lookup()	2013-09-06 13:33:15 -07:00
clk.h	clk: add CLK_SET_RATE_NO_REPARENT flag	2013-08-19 12:27:17 -07:00
Makefile	ARM: S3C64XX: Migrate clock handling to Common Clock Framework	2013-09-17 06:47:36 +09:00