ccac7ce373
Refactor how address space initialization works. Instead of having the address space function create the MMU object (and thus require separate but equal functions for gpummu and iommu) use a single function and pass the MMU struct in. Make the generic code cleaner by using target specific functions to create the address space so a2xx can do its own thing in its own space. For all the other targets use a generic helper to initialize IOMMU but leave the door open for newer targets to use customization if they need it. Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> [squash in rebase fixups] Signed-off-by: Rob Clark <robdclark@chromium.org>
509 lines
17 KiB
C
509 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2018 The Linux Foundation. All rights reserved. */
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#include "a2xx_gpu.h"
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#include "msm_gem.h"
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#include "msm_mmu.h"
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extern bool hang_debug;
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static void a2xx_dump(struct msm_gpu *gpu);
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static bool a2xx_idle(struct msm_gpu *gpu);
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static bool a2xx_me_init(struct msm_gpu *gpu)
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{
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struct msm_ringbuffer *ring = gpu->rb[0];
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OUT_PKT3(ring, CP_ME_INIT, 18);
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/* All fields present (bits 9:0) */
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OUT_RING(ring, 0x000003ff);
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/* Disable/Enable Real-Time Stream processing (present but ignored) */
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OUT_RING(ring, 0x00000000);
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/* Enable (2D <-> 3D) implicit synchronization (present but ignored) */
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, REG_A2XX_RB_SURFACE_INFO - 0x2000);
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OUT_RING(ring, REG_A2XX_PA_SC_WINDOW_OFFSET - 0x2000);
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OUT_RING(ring, REG_A2XX_VGT_MAX_VTX_INDX - 0x2000);
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OUT_RING(ring, REG_A2XX_SQ_PROGRAM_CNTL - 0x2000);
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OUT_RING(ring, REG_A2XX_RB_DEPTHCONTROL - 0x2000);
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OUT_RING(ring, REG_A2XX_PA_SU_POINT_SIZE - 0x2000);
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OUT_RING(ring, REG_A2XX_PA_SC_LINE_CNTL - 0x2000);
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OUT_RING(ring, REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE - 0x2000);
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/* Vertex and Pixel Shader Start Addresses in instructions
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* (3 DWORDS per instruction) */
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OUT_RING(ring, 0x80000180);
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/* Maximum Contexts */
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OUT_RING(ring, 0x00000001);
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/* Write Confirm Interval and The CP will wait the
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* wait_interval * 16 clocks between polling */
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OUT_RING(ring, 0x00000000);
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/* NQ and External Memory Swap */
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OUT_RING(ring, 0x00000000);
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/* protected mode error checking (0x1f2 is REG_AXXX_CP_INT_CNTL) */
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OUT_RING(ring, 0x200001f2);
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/* Disable header dumping and Header dump address */
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OUT_RING(ring, 0x00000000);
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/* Header dump size */
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OUT_RING(ring, 0x00000000);
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/* enable protected mode */
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OUT_PKT3(ring, CP_SET_PROTECTED_MODE, 1);
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OUT_RING(ring, 1);
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gpu->funcs->flush(gpu, ring);
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return a2xx_idle(gpu);
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}
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static int a2xx_hw_init(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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dma_addr_t pt_base, tran_error;
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uint32_t *ptr, len;
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int i, ret;
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msm_gpummu_params(gpu->aspace->mmu, &pt_base, &tran_error);
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DBG("%s", gpu->name);
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/* halt ME to avoid ucode upload issues on a20x */
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gpu_write(gpu, REG_AXXX_CP_ME_CNTL, AXXX_CP_ME_CNTL_HALT);
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gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE1, 0xfffffffe);
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gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, 0xffffffff);
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/* note: kgsl uses 0x00000001 after first reset on a22x */
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gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0xffffffff);
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msleep(30);
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gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0x00000000);
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if (adreno_is_a225(adreno_gpu))
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gpu_write(gpu, REG_A2XX_SQ_FLOW_CONTROL, 0x18000000);
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/* note: kgsl uses 0x0000ffff for a20x */
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gpu_write(gpu, REG_A2XX_RBBM_CNTL, 0x00004442);
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/* MPU: physical range */
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gpu_write(gpu, REG_A2XX_MH_MMU_MPU_BASE, 0x00000000);
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gpu_write(gpu, REG_A2XX_MH_MMU_MPU_END, 0xfffff000);
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gpu_write(gpu, REG_A2XX_MH_MMU_CONFIG, A2XX_MH_MMU_CONFIG_MMU_ENABLE |
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A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(BEH_TRAN_RNG) |
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A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(BEH_TRAN_RNG) |
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A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(BEH_TRAN_RNG) |
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A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(BEH_TRAN_RNG) |
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A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(BEH_TRAN_RNG) |
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A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(BEH_TRAN_RNG) |
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A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(BEH_TRAN_RNG) |
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A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(BEH_TRAN_RNG) |
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A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(BEH_TRAN_RNG) |
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A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(BEH_TRAN_RNG) |
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A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(BEH_TRAN_RNG));
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/* same as parameters in adreno_gpu */
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gpu_write(gpu, REG_A2XX_MH_MMU_VA_RANGE, SZ_16M |
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A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(0xfff));
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gpu_write(gpu, REG_A2XX_MH_MMU_PT_BASE, pt_base);
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gpu_write(gpu, REG_A2XX_MH_MMU_TRAN_ERROR, tran_error);
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gpu_write(gpu, REG_A2XX_MH_MMU_INVALIDATE,
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A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL |
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A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC);
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gpu_write(gpu, REG_A2XX_MH_ARBITER_CONFIG,
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A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(16) |
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A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE |
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A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE |
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A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(1) |
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A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE |
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A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE |
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A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE |
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A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(8) |
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A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE |
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A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE |
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A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE |
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A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE |
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A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE);
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if (!adreno_is_a20x(adreno_gpu))
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gpu_write(gpu, REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1, 0x00032f07);
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gpu_write(gpu, REG_A2XX_SQ_VS_PROGRAM, 0x00000000);
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gpu_write(gpu, REG_A2XX_SQ_PS_PROGRAM, 0x00000000);
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gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE1, 0); /* 0x200 for msm8960? */
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gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, 0); /* 0x80/0x1a0 for a22x? */
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/* note: gsl doesn't set this */
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gpu_write(gpu, REG_A2XX_RBBM_DEBUG, 0x00080000);
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gpu_write(gpu, REG_A2XX_RBBM_INT_CNTL,
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A2XX_RBBM_INT_CNTL_RDERR_INT_MASK);
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gpu_write(gpu, REG_AXXX_CP_INT_CNTL,
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AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK |
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AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK |
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AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK |
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AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK |
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AXXX_CP_INT_CNTL_IB_ERROR_MASK |
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AXXX_CP_INT_CNTL_IB1_INT_MASK |
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AXXX_CP_INT_CNTL_RB_INT_MASK);
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gpu_write(gpu, REG_A2XX_SQ_INT_CNTL, 0);
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gpu_write(gpu, REG_A2XX_MH_INTERRUPT_MASK,
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A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR |
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A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR |
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A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT);
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for (i = 3; i <= 5; i++)
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if ((SZ_16K << i) == adreno_gpu->gmem)
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break;
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gpu_write(gpu, REG_A2XX_RB_EDRAM_INFO, i);
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ret = adreno_hw_init(gpu);
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if (ret)
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return ret;
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/* NOTE: PM4/micro-engine firmware registers look to be the same
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* for a2xx and a3xx.. we could possibly push that part down to
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* adreno_gpu base class. Or push both PM4 and PFP but
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* parameterize the pfp ucode addr/data registers..
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*/
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/* Load PM4: */
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ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PM4]->data);
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len = adreno_gpu->fw[ADRENO_FW_PM4]->size / 4;
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DBG("loading PM4 ucode version: %x", ptr[1]);
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gpu_write(gpu, REG_AXXX_CP_DEBUG,
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AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE);
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gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0);
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for (i = 1; i < len; i++)
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gpu_write(gpu, REG_AXXX_CP_ME_RAM_DATA, ptr[i]);
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/* Load PFP: */
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ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PFP]->data);
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len = adreno_gpu->fw[ADRENO_FW_PFP]->size / 4;
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DBG("loading PFP ucode version: %x", ptr[5]);
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gpu_write(gpu, REG_A2XX_CP_PFP_UCODE_ADDR, 0);
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for (i = 1; i < len; i++)
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gpu_write(gpu, REG_A2XX_CP_PFP_UCODE_DATA, ptr[i]);
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gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, 0x000C0804);
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/* clear ME_HALT to start micro engine */
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gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0);
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return a2xx_me_init(gpu) ? 0 : -EINVAL;
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}
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static void a2xx_recover(struct msm_gpu *gpu)
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{
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int i;
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adreno_dump_info(gpu);
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for (i = 0; i < 8; i++) {
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printk("CP_SCRATCH_REG%d: %u\n", i,
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gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i));
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}
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/* dump registers before resetting gpu, if enabled: */
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if (hang_debug)
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a2xx_dump(gpu);
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gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 1);
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gpu_read(gpu, REG_A2XX_RBBM_SOFT_RESET);
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gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0);
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adreno_recover(gpu);
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}
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static void a2xx_destroy(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct a2xx_gpu *a2xx_gpu = to_a2xx_gpu(adreno_gpu);
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DBG("%s", gpu->name);
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adreno_gpu_cleanup(adreno_gpu);
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kfree(a2xx_gpu);
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}
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static bool a2xx_idle(struct msm_gpu *gpu)
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{
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/* wait for ringbuffer to drain: */
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if (!adreno_idle(gpu, gpu->rb[0]))
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return false;
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/* then wait for GPU to finish: */
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if (spin_until(!(gpu_read(gpu, REG_A2XX_RBBM_STATUS) &
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A2XX_RBBM_STATUS_GUI_ACTIVE))) {
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DRM_ERROR("%s: timeout waiting for GPU to idle!\n", gpu->name);
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/* TODO maybe we need to reset GPU here to recover from hang? */
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return false;
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}
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return true;
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}
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static irqreturn_t a2xx_irq(struct msm_gpu *gpu)
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{
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uint32_t mstatus, status;
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mstatus = gpu_read(gpu, REG_A2XX_MASTER_INT_SIGNAL);
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if (mstatus & A2XX_MASTER_INT_SIGNAL_MH_INT_STAT) {
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status = gpu_read(gpu, REG_A2XX_MH_INTERRUPT_STATUS);
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dev_warn(gpu->dev->dev, "MH_INT: %08X\n", status);
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dev_warn(gpu->dev->dev, "MMU_PAGE_FAULT: %08X\n",
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gpu_read(gpu, REG_A2XX_MH_MMU_PAGE_FAULT));
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gpu_write(gpu, REG_A2XX_MH_INTERRUPT_CLEAR, status);
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}
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if (mstatus & A2XX_MASTER_INT_SIGNAL_CP_INT_STAT) {
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status = gpu_read(gpu, REG_AXXX_CP_INT_STATUS);
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/* only RB_INT is expected */
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if (status & ~AXXX_CP_INT_CNTL_RB_INT_MASK)
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dev_warn(gpu->dev->dev, "CP_INT: %08X\n", status);
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gpu_write(gpu, REG_AXXX_CP_INT_ACK, status);
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}
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if (mstatus & A2XX_MASTER_INT_SIGNAL_RBBM_INT_STAT) {
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status = gpu_read(gpu, REG_A2XX_RBBM_INT_STATUS);
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dev_warn(gpu->dev->dev, "RBBM_INT: %08X\n", status);
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gpu_write(gpu, REG_A2XX_RBBM_INT_ACK, status);
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}
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msm_gpu_retire(gpu);
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return IRQ_HANDLED;
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}
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static const unsigned int a200_registers[] = {
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0x0000, 0x0002, 0x0004, 0x000B, 0x003B, 0x003D, 0x0040, 0x0044,
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0x0046, 0x0047, 0x01C0, 0x01C1, 0x01C3, 0x01C8, 0x01D5, 0x01D9,
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0x01DC, 0x01DD, 0x01EA, 0x01EA, 0x01EE, 0x01F3, 0x01F6, 0x01F7,
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0x01FC, 0x01FF, 0x0391, 0x0392, 0x039B, 0x039E, 0x03B2, 0x03B5,
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0x03B7, 0x03B7, 0x03F8, 0x03FB, 0x0440, 0x0440, 0x0443, 0x0444,
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0x044B, 0x044B, 0x044D, 0x044F, 0x0452, 0x0452, 0x0454, 0x045B,
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0x047F, 0x047F, 0x0578, 0x0587, 0x05C9, 0x05C9, 0x05D0, 0x05D0,
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0x0601, 0x0604, 0x0606, 0x0609, 0x060B, 0x060E, 0x0613, 0x0614,
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0x0A29, 0x0A2B, 0x0A2F, 0x0A31, 0x0A40, 0x0A43, 0x0A45, 0x0A45,
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0x0A4E, 0x0A4F, 0x0C2C, 0x0C2C, 0x0C30, 0x0C30, 0x0C38, 0x0C3C,
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0x0C40, 0x0C40, 0x0C44, 0x0C44, 0x0C80, 0x0C86, 0x0C88, 0x0C94,
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0x0C99, 0x0C9A, 0x0CA4, 0x0CA5, 0x0D00, 0x0D03, 0x0D06, 0x0D06,
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0x0D08, 0x0D0B, 0x0D34, 0x0D35, 0x0DAE, 0x0DC1, 0x0DC8, 0x0DD4,
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0x0DD8, 0x0DD9, 0x0E00, 0x0E00, 0x0E02, 0x0E04, 0x0E17, 0x0E1E,
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0x0EC0, 0x0EC9, 0x0ECB, 0x0ECC, 0x0ED0, 0x0ED0, 0x0ED4, 0x0ED7,
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0x0EE0, 0x0EE2, 0x0F01, 0x0F02, 0x0F0C, 0x0F0C, 0x0F0E, 0x0F12,
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0x0F26, 0x0F2A, 0x0F2C, 0x0F2C, 0x2000, 0x2002, 0x2006, 0x200F,
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0x2080, 0x2082, 0x2100, 0x2109, 0x210C, 0x2114, 0x2180, 0x2184,
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0x21F5, 0x21F7, 0x2200, 0x2208, 0x2280, 0x2283, 0x2293, 0x2294,
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0x2300, 0x2308, 0x2312, 0x2312, 0x2316, 0x231D, 0x2324, 0x2326,
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0x2380, 0x2383, 0x2400, 0x2402, 0x2406, 0x240F, 0x2480, 0x2482,
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0x2500, 0x2509, 0x250C, 0x2514, 0x2580, 0x2584, 0x25F5, 0x25F7,
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0x2600, 0x2608, 0x2680, 0x2683, 0x2693, 0x2694, 0x2700, 0x2708,
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0x2712, 0x2712, 0x2716, 0x271D, 0x2724, 0x2726, 0x2780, 0x2783,
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0x4000, 0x4003, 0x4800, 0x4805, 0x4900, 0x4900, 0x4908, 0x4908,
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~0 /* sentinel */
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};
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static const unsigned int a220_registers[] = {
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0x0000, 0x0002, 0x0004, 0x000B, 0x003B, 0x003D, 0x0040, 0x0044,
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0x0046, 0x0047, 0x01C0, 0x01C1, 0x01C3, 0x01C8, 0x01D5, 0x01D9,
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0x01DC, 0x01DD, 0x01EA, 0x01EA, 0x01EE, 0x01F3, 0x01F6, 0x01F7,
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0x01FC, 0x01FF, 0x0391, 0x0392, 0x039B, 0x039E, 0x03B2, 0x03B5,
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0x03B7, 0x03B7, 0x03F8, 0x03FB, 0x0440, 0x0440, 0x0443, 0x0444,
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0x044B, 0x044B, 0x044D, 0x044F, 0x0452, 0x0452, 0x0454, 0x045B,
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0x047F, 0x047F, 0x0578, 0x0587, 0x05C9, 0x05C9, 0x05D0, 0x05D0,
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0x0601, 0x0604, 0x0606, 0x0609, 0x060B, 0x060E, 0x0613, 0x0614,
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0x0A29, 0x0A2B, 0x0A2F, 0x0A31, 0x0A40, 0x0A40, 0x0A42, 0x0A43,
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0x0A45, 0x0A45, 0x0A4E, 0x0A4F, 0x0C30, 0x0C30, 0x0C38, 0x0C39,
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0x0C3C, 0x0C3C, 0x0C80, 0x0C81, 0x0C88, 0x0C93, 0x0D00, 0x0D03,
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0x0D05, 0x0D06, 0x0D08, 0x0D0B, 0x0D34, 0x0D35, 0x0DAE, 0x0DC1,
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0x0DC8, 0x0DD4, 0x0DD8, 0x0DD9, 0x0E00, 0x0E00, 0x0E02, 0x0E04,
|
|
0x0E17, 0x0E1E, 0x0EC0, 0x0EC9, 0x0ECB, 0x0ECC, 0x0ED0, 0x0ED0,
|
|
0x0ED4, 0x0ED7, 0x0EE0, 0x0EE2, 0x0F01, 0x0F02, 0x2000, 0x2002,
|
|
0x2006, 0x200F, 0x2080, 0x2082, 0x2100, 0x2102, 0x2104, 0x2109,
|
|
0x210C, 0x2114, 0x2180, 0x2184, 0x21F5, 0x21F7, 0x2200, 0x2202,
|
|
0x2204, 0x2204, 0x2208, 0x2208, 0x2280, 0x2282, 0x2294, 0x2294,
|
|
0x2300, 0x2308, 0x2309, 0x230A, 0x2312, 0x2312, 0x2316, 0x2316,
|
|
0x2318, 0x231D, 0x2324, 0x2326, 0x2380, 0x2383, 0x2400, 0x2402,
|
|
0x2406, 0x240F, 0x2480, 0x2482, 0x2500, 0x2502, 0x2504, 0x2509,
|
|
0x250C, 0x2514, 0x2580, 0x2584, 0x25F5, 0x25F7, 0x2600, 0x2602,
|
|
0x2604, 0x2606, 0x2608, 0x2608, 0x2680, 0x2682, 0x2694, 0x2694,
|
|
0x2700, 0x2708, 0x2712, 0x2712, 0x2716, 0x2716, 0x2718, 0x271D,
|
|
0x2724, 0x2726, 0x2780, 0x2783, 0x4000, 0x4003, 0x4800, 0x4805,
|
|
0x4900, 0x4900, 0x4908, 0x4908,
|
|
~0 /* sentinel */
|
|
};
|
|
|
|
static const unsigned int a225_registers[] = {
|
|
0x0000, 0x0002, 0x0004, 0x000B, 0x003B, 0x003D, 0x0040, 0x0044,
|
|
0x0046, 0x0047, 0x013C, 0x013C, 0x0140, 0x014F, 0x01C0, 0x01C1,
|
|
0x01C3, 0x01C8, 0x01D5, 0x01D9, 0x01DC, 0x01DD, 0x01EA, 0x01EA,
|
|
0x01EE, 0x01F3, 0x01F6, 0x01F7, 0x01FC, 0x01FF, 0x0391, 0x0392,
|
|
0x039B, 0x039E, 0x03B2, 0x03B5, 0x03B7, 0x03B7, 0x03F8, 0x03FB,
|
|
0x0440, 0x0440, 0x0443, 0x0444, 0x044B, 0x044B, 0x044D, 0x044F,
|
|
0x0452, 0x0452, 0x0454, 0x045B, 0x047F, 0x047F, 0x0578, 0x0587,
|
|
0x05C9, 0x05C9, 0x05D0, 0x05D0, 0x0601, 0x0604, 0x0606, 0x0609,
|
|
0x060B, 0x060E, 0x0613, 0x0614, 0x0A29, 0x0A2B, 0x0A2F, 0x0A31,
|
|
0x0A40, 0x0A40, 0x0A42, 0x0A43, 0x0A45, 0x0A45, 0x0A4E, 0x0A4F,
|
|
0x0C01, 0x0C1D, 0x0C30, 0x0C30, 0x0C38, 0x0C39, 0x0C3C, 0x0C3C,
|
|
0x0C80, 0x0C81, 0x0C88, 0x0C93, 0x0D00, 0x0D03, 0x0D05, 0x0D06,
|
|
0x0D08, 0x0D0B, 0x0D34, 0x0D35, 0x0DAE, 0x0DC1, 0x0DC8, 0x0DD4,
|
|
0x0DD8, 0x0DD9, 0x0E00, 0x0E00, 0x0E02, 0x0E04, 0x0E17, 0x0E1E,
|
|
0x0EC0, 0x0EC9, 0x0ECB, 0x0ECC, 0x0ED0, 0x0ED0, 0x0ED4, 0x0ED7,
|
|
0x0EE0, 0x0EE2, 0x0F01, 0x0F02, 0x2000, 0x200F, 0x2080, 0x2082,
|
|
0x2100, 0x2109, 0x210C, 0x2114, 0x2180, 0x2184, 0x21F5, 0x21F7,
|
|
0x2200, 0x2202, 0x2204, 0x2206, 0x2208, 0x2210, 0x2220, 0x2222,
|
|
0x2280, 0x2282, 0x2294, 0x2294, 0x2297, 0x2297, 0x2300, 0x230A,
|
|
0x2312, 0x2312, 0x2315, 0x2316, 0x2318, 0x231D, 0x2324, 0x2326,
|
|
0x2340, 0x2357, 0x2360, 0x2360, 0x2380, 0x2383, 0x2400, 0x240F,
|
|
0x2480, 0x2482, 0x2500, 0x2509, 0x250C, 0x2514, 0x2580, 0x2584,
|
|
0x25F5, 0x25F7, 0x2600, 0x2602, 0x2604, 0x2606, 0x2608, 0x2610,
|
|
0x2620, 0x2622, 0x2680, 0x2682, 0x2694, 0x2694, 0x2697, 0x2697,
|
|
0x2700, 0x270A, 0x2712, 0x2712, 0x2715, 0x2716, 0x2718, 0x271D,
|
|
0x2724, 0x2726, 0x2740, 0x2757, 0x2760, 0x2760, 0x2780, 0x2783,
|
|
0x4000, 0x4003, 0x4800, 0x4806, 0x4808, 0x4808, 0x4900, 0x4900,
|
|
0x4908, 0x4908,
|
|
~0 /* sentinel */
|
|
};
|
|
|
|
/* would be nice to not have to duplicate the _show() stuff with printk(): */
|
|
static void a2xx_dump(struct msm_gpu *gpu)
|
|
{
|
|
printk("status: %08x\n",
|
|
gpu_read(gpu, REG_A2XX_RBBM_STATUS));
|
|
adreno_dump(gpu);
|
|
}
|
|
|
|
static struct msm_gpu_state *a2xx_gpu_state_get(struct msm_gpu *gpu)
|
|
{
|
|
struct msm_gpu_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
|
|
|
|
if (!state)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
adreno_gpu_state_get(gpu, state);
|
|
|
|
state->rbbm_status = gpu_read(gpu, REG_A2XX_RBBM_STATUS);
|
|
|
|
return state;
|
|
}
|
|
|
|
static struct msm_gem_address_space *
|
|
a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
|
|
{
|
|
struct msm_mmu *mmu = msm_gpummu_new(&pdev->dev, gpu);
|
|
struct msm_gem_address_space *aspace;
|
|
|
|
aspace = msm_gem_address_space_create(mmu, "gpu", SZ_16M,
|
|
SZ_16M + 0xfff * SZ_64K);
|
|
|
|
if (IS_ERR(aspace) && !IS_ERR(mmu))
|
|
mmu->funcs->destroy(mmu);
|
|
|
|
return aspace;
|
|
}
|
|
|
|
/* Register offset defines for A2XX - copy of A3XX */
|
|
static const unsigned int a2xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
|
|
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE),
|
|
REG_ADRENO_SKIP(REG_ADRENO_CP_RB_BASE_HI),
|
|
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_AXXX_CP_RB_RPTR_ADDR),
|
|
REG_ADRENO_SKIP(REG_ADRENO_CP_RB_RPTR_ADDR_HI),
|
|
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_AXXX_CP_RB_RPTR),
|
|
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_AXXX_CP_RB_WPTR),
|
|
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_AXXX_CP_RB_CNTL),
|
|
};
|
|
|
|
static const struct adreno_gpu_funcs funcs = {
|
|
.base = {
|
|
.get_param = adreno_get_param,
|
|
.hw_init = a2xx_hw_init,
|
|
.pm_suspend = msm_gpu_pm_suspend,
|
|
.pm_resume = msm_gpu_pm_resume,
|
|
.recover = a2xx_recover,
|
|
.submit = adreno_submit,
|
|
.flush = adreno_flush,
|
|
.active_ring = adreno_active_ring,
|
|
.irq = a2xx_irq,
|
|
.destroy = a2xx_destroy,
|
|
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
|
|
.show = adreno_show,
|
|
#endif
|
|
.gpu_state_get = a2xx_gpu_state_get,
|
|
.gpu_state_put = adreno_gpu_state_put,
|
|
.create_address_space = a2xx_create_address_space,
|
|
},
|
|
};
|
|
|
|
static const struct msm_gpu_perfcntr perfcntrs[] = {
|
|
/* TODO */
|
|
};
|
|
|
|
struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
|
|
{
|
|
struct a2xx_gpu *a2xx_gpu = NULL;
|
|
struct adreno_gpu *adreno_gpu;
|
|
struct msm_gpu *gpu;
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
struct platform_device *pdev = priv->gpu_pdev;
|
|
int ret;
|
|
|
|
if (!pdev) {
|
|
dev_err(dev->dev, "no a2xx device\n");
|
|
ret = -ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
a2xx_gpu = kzalloc(sizeof(*a2xx_gpu), GFP_KERNEL);
|
|
if (!a2xx_gpu) {
|
|
ret = -ENOMEM;
|
|
goto fail;
|
|
}
|
|
|
|
adreno_gpu = &a2xx_gpu->base;
|
|
gpu = &adreno_gpu->base;
|
|
|
|
gpu->perfcntrs = perfcntrs;
|
|
gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
|
|
|
|
if (adreno_is_a20x(adreno_gpu))
|
|
adreno_gpu->registers = a200_registers;
|
|
else if (adreno_is_a225(adreno_gpu))
|
|
adreno_gpu->registers = a225_registers;
|
|
else
|
|
adreno_gpu->registers = a220_registers;
|
|
|
|
adreno_gpu->reg_offsets = a2xx_register_offsets;
|
|
|
|
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
if (!gpu->aspace) {
|
|
dev_err(dev->dev, "No memory protection without MMU\n");
|
|
ret = -ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
return gpu;
|
|
|
|
fail:
|
|
if (a2xx_gpu)
|
|
a2xx_destroy(&a2xx_gpu->base.base);
|
|
|
|
return ERR_PTR(ret);
|
|
}
|