The datasheet is a bit confusing about this. It says that a dataword has 4
leading zeros, but the first zero is already put on the bus when CS is pulled
low and the second zero is put on the bus on the first leading edge of SCLK, so
when the first bit is sampled on the first trailing edge it will sample what the
datasheet refers to as the second leading zero. Subsequently we only see 3
leading zeros in the 16 bit dataword and the result we get is shifted to the
left by one bit. Fix this by adjusting the channel shift by 1.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
cb75f2335c