Yakir Yang cb5571fcf8 drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1 ... There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced by commit bcec20fd5a ("drm: bridge: analogix/dp: add some rk3288 special registers setting"). The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1 BIT 0, not BIT 1. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Reviewed-by: Tomasz Figa <tomasz.figa@chromium.com> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>		2016-07-05 09:16:38 +08:00
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drm	drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1	2016-07-05 09:16:38 +08:00
host1x	remove lots of IS_ERR_VALUE abuses	2016-05-27 15:26:11 -07:00
ipu-v3	drm/imx: Match imx-ipuv3-crtc components using device node in platform data	2016-05-23 12:35:11 +02:00
vga	vga_switcheroo: Support deferred probing of audio clients	2016-05-31 13:16:22 +02:00
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