cb42e20ea0
Some architectures don't use the common clock framework and don't implement all the clk interfaces for every clock. This is the case for da850-lcdk where clk_set_rate() only works for PLL0 and PLL1. Trying to set the clock rate for the LCDC clock results in -EINVAL being returned. As a workaround for that: if the call to clk_set_rate() fails, fall back to adjusting the clock divider instead. Proper divider value is calculated by dividing the current clock rate by the required pixel clock rate in HZ. This code is based on a hack initially developed internally for baylibre by Karl Beldan <kbeldan@baylibre.com>. Tested with a da850-lcdk with an LCD display connected over VGA. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Jyri Sarha <jsarha@ti.com> |
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| drm | ||
| host1x | ||
| ipu-v3 | ||
| vga | ||
| Makefile | ||