53e155f2bb
+ usual progress on cleanups
+ dsi vs EPROBE_DEFER fixes
+ msm8998 (snapdragon 835 support)
+ a540 gpu support (mesa support already landed)
+ dsi, dsi-phy support
+ mdp5 and dpu interconnect (bus/memory scaling) support
+ initial prep work for per-context pagetables (at least the parts that
don't have external dependencies like iommu/arm-smmu)
There is one more patch for fixing DSI cmd mode panels (part of a set of
patches to get things working on nexus5), but it would be conflicty with
1cff7440a8 in drm-next without rebasing or back-merge,
and since it doesn't conflict with anything in msm-next, I think it best
if Sean merges that through drm-mix-fixes instead.
(In other news, I've been making some progress w/ getting efifb working
properly on sdm850 laptop without horrible hacks, and drm/msm + clk stuff
not totally falling over when bootloader enables display and things are
already running when driver probes.. but not quite ready yet, hopefully
we can post some of that for 5.4.. should help for both the sdm835 and
sdm850 laptops.)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGsj3N4XzDLSDoa+4RHZ9wXObYmhcep0M3LjnRg48BeLvg@mail.gmail.com
109 lines
2.8 KiB
C
109 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*/
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#ifndef __DSI_PHY_H__
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#define __DSI_PHY_H__
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#include <linux/regulator/consumer.h>
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#include "dsi.h"
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#define dsi_phy_read(offset) msm_readl((offset))
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#define dsi_phy_write(offset, data) msm_writel((data), (offset))
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/* v3.0.0 10nm implementation that requires the old timings settings */
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#define V3_0_0_10NM_OLD_TIMINGS_QUIRK BIT(0)
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struct msm_dsi_phy_ops {
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int (*init) (struct msm_dsi_phy *phy);
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int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
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struct msm_dsi_phy_clk_request *clk_req);
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void (*disable)(struct msm_dsi_phy *phy);
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};
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struct msm_dsi_phy_cfg {
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enum msm_dsi_phy_type type;
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struct dsi_reg_config reg_cfg;
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struct msm_dsi_phy_ops ops;
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/*
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* Each cell {phy_id, pll_id} of the truth table indicates
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* if the source PLL selection bit should be set for each PHY.
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* Fill default H/W values in illegal cells, eg. cell {0, 1}.
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*/
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bool src_pll_truthtable[DSI_MAX][DSI_MAX];
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const resource_size_t io_start[DSI_MAX];
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const int num_dsi_phy;
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const int quirks;
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};
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
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struct msm_dsi_dphy_timing {
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u32 clk_pre;
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u32 clk_post;
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u32 clk_zero;
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u32 clk_trail;
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u32 clk_prepare;
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u32 hs_exit;
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u32 hs_zero;
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u32 hs_prepare;
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u32 hs_trail;
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u32 hs_rqst;
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u32 ta_go;
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u32 ta_sure;
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u32 ta_get;
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struct msm_dsi_phy_shared_timings shared_timings;
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/* For PHY v2 only */
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u32 hs_rqst_ckln;
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u32 hs_prep_dly;
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u32 hs_prep_dly_ckln;
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u8 hs_halfbyte_en;
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u8 hs_halfbyte_en_ckln;
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};
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struct msm_dsi_phy {
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struct platform_device *pdev;
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void __iomem *base;
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void __iomem *reg_base;
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void __iomem *lane_base;
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int id;
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struct clk *ahb_clk;
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struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
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struct msm_dsi_dphy_timing timing;
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const struct msm_dsi_phy_cfg *cfg;
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enum msm_dsi_phy_usecase usecase;
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bool regulator_ldo_mode;
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struct msm_dsi_pll *pll;
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};
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/*
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* PHY internal functions
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*/
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int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req);
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void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
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u32 bit_mask);
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int msm_dsi_phy_init_common(struct msm_dsi_phy *phy);
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#endif /* __DSI_PHY_H__ */
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