Dmytro Laktyushkin cb0eca01ad drm/amd/display: fix dcn315 memory channel count and width read ...

[Why & How]
Correctly set ddr5 channel width to 8 bytes

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2022-09-21 17:18:39 -04:00

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acp

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amdgpu

drm/amdgpu: Update PTE flags with TF enabled

2022-09-21 17:14:09 -04:00

amdkfd

drm/amdkfd: Fix isa version for the GC 10.3.7

2022-08-25 13:54:08 -04:00

display

drm/amd/display: fix dcn315 memory channel count and width read

2022-09-21 17:18:39 -04:00

include

drm/amdgpu: Update mes_v11_api_def.h

2022-08-30 16:56:21 -04:00

pm

drm/amd/pm: disable BACO entry/exit completely on several sienna cichlid cards

2022-09-13 14:25:39 -04:00