Lendacky, Thomas 9916716a1b amd-xgbe: Prepare for more fine grained cache coherency controls ...

In prep for setting fine grained read and write DMA cache coherency
controls, allow specific values to be used to set the cache coherency
registers.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

2017-06-29 15:14:18 -04:00

19 KiB

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