25fdd5933e
SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a
top level wrapper consisting of Display Processing Unit (DPU) and
display peripheral modules such as Display Serial Interface (DSI)
and DisplayPort (DP).
MDSS functions essentially as a back-end composition engine. It blends
video and graphic images stored in the frame buffers and scans out the
composed image to a display sink (over DSI/DP).
The following diagram represents hardware blocks for a simple pipeline
(two planes are present on a given crtc which is connected to a DSI
connector):
MDSS
+---------------------------------+
| +-----------------------------+ |
| | DPU | |
| | +--------+ +--------+ | |
| | | SSPP | | SSPP | | |
| | +----+---+ +----+---+ | |
| | | | | |
| | +----v-----------v---+ | |
| | | Layer Mixer (LM) | | |
| | +--------------------+ | |
| | +--------------------+ | |
| | | PingPong (PP) | | |
| | +--------------------+ | |
| | +--------------------+ | |
| | | INTERFACE (VIDEO) | | |
| | +---+----------------+ | |
| +------|----------------------+ |
| | |
| +------|---------------------+ |
| | | DISPLAY PERIPHERALS | |
| | +---v-+ +-----+ | |
| | | DSI | | DP | | |
| | +-----+ +-----+ | |
| +----------------------------+ |
+---------------------------------+
The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs)
depends on SoC capabilities.
Overview of DPU sub-blocks:
---------------------------
* Source Surface Processor (SSPP):
Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are
capable of performing format conversion, scaling and quality improvement
for source surfaces.
* Layer Mixer (LM):
Blend source surfaces together (in requested zorder)
* PingPong (PP):
This block controls frame done interrupt output, EOL and EOF generation,
overflow/underflow control.
* Display interface (INTF):
Timing generator and interface connecting the display peripherals.
DRM components mapping to DPU architecture:
------------------------------------------
PLANEs maps to SSPPs
CRTC maps to LMs
Encoder maps to PPs, INTFs
Data flow setup:
---------------
MDSS hardware can support various data flows (e.g.):
- Dual pipe: Output from two LMs combined to single display.
- Split display: Output from two LMs connected to two separate
interfaces.
The hardware capabilities determine the number of concurrent data paths
possible. Any control path (i.e. pipeline w/i DPU) can be routed to any
of the hardware data paths. A given control path can be triggered,
flushed and controlled independently.
Changes in v3:
- Move msm_media_info.h from uapi to dpu/ subdir
- Remove preclose callback dpu (it's handled in core)
- Fix kbuild warnings with parent_ops
- Remove unused functions from dpu_core_irq
- Rename mdss_phys to mdss
- Rename mdp_phys address space to mdp
- Drop _phys from vbif and regdma binding names
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org>
Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
[robclark minor rebase]
Signed-off-by: Rob Clark <robdclark@gmail.com>
57 lines
2.2 KiB
C
57 lines
2.2 KiB
C
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DPU_HWIO_H
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#define _DPU_HWIO_H
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#include "dpu_hw_util.h"
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/**
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* MDP TOP block Register and bit fields and defines
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*/
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#define DISP_INTF_SEL 0x004
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#define INTR_EN 0x010
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#define INTR_STATUS 0x014
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#define INTR_CLEAR 0x018
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#define INTR2_EN 0x008
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#define INTR2_STATUS 0x00c
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#define INTR2_CLEAR 0x02c
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#define HIST_INTR_EN 0x01c
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#define HIST_INTR_STATUS 0x020
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#define HIST_INTR_CLEAR 0x024
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#define INTF_INTR_EN 0x1C0
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#define INTF_INTR_STATUS 0x1C4
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#define INTF_INTR_CLEAR 0x1C8
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#define SPLIT_DISPLAY_EN 0x2F4
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#define SPLIT_DISPLAY_UPPER_PIPE_CTRL 0x2F8
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#define DSPP_IGC_COLOR0_RAM_LUTN 0x300
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#define DSPP_IGC_COLOR1_RAM_LUTN 0x304
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#define DSPP_IGC_COLOR2_RAM_LUTN 0x308
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#define HW_EVENTS_CTL 0x37C
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#define CLK_CTRL3 0x3A8
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#define CLK_STATUS3 0x3AC
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#define CLK_CTRL4 0x3B0
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#define CLK_STATUS4 0x3B4
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#define CLK_CTRL5 0x3B8
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#define CLK_STATUS5 0x3BC
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#define CLK_CTRL7 0x3D0
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#define CLK_STATUS7 0x3D4
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#define SPLIT_DISPLAY_LOWER_PIPE_CTRL 0x3F0
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#define SPLIT_DISPLAY_TE_LINE_INTERVAL 0x3F4
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#define INTF_SW_RESET_MASK 0x3FC
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#define HDMI_DP_CORE_SELECT 0x408
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#define MDP_OUT_CTL_0 0x410
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#define MDP_VSYNC_SEL 0x414
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#define DCE_SEL 0x450
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#endif /*_DPU_HWIO_H */
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