c8fe6a6811
This patch introduces vGPU interrupt emulation framework. The vGPU intrerrupt emulation framework is an event-based interrupt emulation framework. It's responsible for emulating GEN hardware interrupts during emulating other HW behaviour. It consists several components: - Descriptions of interrupt register bit - Upper level <-> lower level interrupt mapping - GEN HW IER/IMR/IIR register emulation routines - Event-based interrupt propagation interface When a GVT-g component wants to inject an interrupt to a VM during a emulation, first it should specify the event needs to be emulated and the framework will deal with the rest of emulation: - Generating related virtual IIR bit according to virtual IER and IMRs, - Generate related virtual upper level virtual IIR bit accodring to the per-platform interrupt mapping - Injecting a MSI to VM Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
121 lines
3.7 KiB
C
121 lines
3.7 KiB
C
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Eddie Dong <eddie.dong@intel.com>
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* Dexuan Cui
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* Jike Song <jike.song@intel.com>
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*
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* Contributors:
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* Zhi Wang <zhi.a.wang@intel.com>
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*
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*/
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#ifndef _GVT_MPT_H_
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#define _GVT_MPT_H_
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/**
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* DOC: Hypervisor Service APIs for GVT-g Core Logic
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*
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* This is the glue layer between specific hypervisor MPT modules and GVT-g core
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* logic. Each kind of hypervisor MPT module provides a collection of function
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* callbacks and will be attached to GVT host when the driver is loading.
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* GVT-g core logic will call these APIs to request specific services from
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* hypervisor.
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*/
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/**
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* intel_gvt_hypervisor_detect_host - check if GVT-g is running within
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* hypervisor host/privilged domain
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*
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* Returns:
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* Zero on success, -ENODEV if current kernel is running inside a VM
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*/
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static inline int intel_gvt_hypervisor_detect_host(void)
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{
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return intel_gvt_host.mpt->detect_host();
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}
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/**
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* intel_gvt_hypervisor_attach_vgpu - call hypervisor to initialize vGPU
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* related stuffs inside hypervisor.
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*
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* Returns:
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* Zero on success, negative error code if failed.
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*/
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static inline int intel_gvt_hypervisor_attach_vgpu(struct intel_vgpu *vgpu)
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{
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return intel_gvt_host.mpt->attach_vgpu(vgpu, &vgpu->handle);
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}
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/**
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* intel_gvt_hypervisor_detach_vgpu - call hypervisor to release vGPU
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* related stuffs inside hypervisor.
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*
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* Returns:
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* Zero on success, negative error code if failed.
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*/
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static inline void intel_gvt_hypervisor_detach_vgpu(struct intel_vgpu *vgpu)
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{
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intel_gvt_host.mpt->detach_vgpu(vgpu->handle);
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}
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#define MSI_CAP_CONTROL(offset) (offset + 2)
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#define MSI_CAP_ADDRESS(offset) (offset + 4)
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#define MSI_CAP_DATA(offset) (offset + 8)
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#define MSI_CAP_EN 0x1
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/**
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* intel_gvt_hypervisor_inject_msi - inject a MSI interrupt into vGPU
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*
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* Returns:
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* Zero on success, negative error code if failed.
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*/
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static inline int intel_gvt_hypervisor_inject_msi(struct intel_vgpu *vgpu)
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{
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unsigned long offset = vgpu->gvt->device_info.msi_cap_offset;
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u16 control, data;
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u32 addr;
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int ret;
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control = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_CONTROL(offset));
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addr = *(u32 *)(vgpu_cfg_space(vgpu) + MSI_CAP_ADDRESS(offset));
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data = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_DATA(offset));
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/* Do not generate MSI if MSIEN is disable */
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if (!(control & MSI_CAP_EN))
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return 0;
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if (WARN(control & GENMASK(15, 1), "only support one MSI format\n"))
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return -EINVAL;
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gvt_dbg_irq("vgpu%d: inject msi address %x data%x\n", vgpu->id, addr,
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data);
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ret = intel_gvt_host.mpt->inject_msi(vgpu->handle, addr, data);
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if (ret)
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return ret;
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return 0;
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}
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#endif /* _GVT_MPT_H_ */
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