1. Remove separate ARCH_EXYNOS7 symbol and consolidate it into one ARCH_EXYNOS. This depends on clk tree: removal of last presence of ARCH_EXYNOS7. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWz5PsAAoJEME3ZuaGi4PX49cP/jhU8jtgdXvzysVITUPi5Ukv Rl82rmCrrX//z6n2LpHaqG/bg1ynOeaRa8TLYU/4gQ53fORmk4UgtqNvC54/2+KX 2CNdNko85oX7DIc2nr5RwTNEBspYh0lTvChZtzQqoKVRdMJSiv2Ms5FcnMNYDt5q xGlQoriTCzlZjt2q6hjlmSZgy8RIn1EeiwsnP3DzmdiX+POgpItfwKln9Ci7E+oz xGa4N/rdQOA0MeV/wizDyWcaCi8HJSDQfMBq6rvx/NtYSGmJORUggFjmmhfp6wAr tuVMflDX20ZoDrP5XptbHapoTtOpQny/D7TiFhWvNZc59zpLei1GJOUOhWdq1PVH om2D59GZ+cNEzDSM/frJiT7VzB32/d479T8DfrwzUahDC2bj+yDPfSK73T72cERs /eBORjYrjM3h9IEwB4DbE6QrxHondXw3B2PQLq4+40w2sE4efupkiBn6vVKUIT9S Za2n6l1W1D2XQawz37Ya2/rAybkMaTIURgsRXE/Oe7GKz11pS3oRmYSeDWcOnMsw PnVL6uTz5zAtoVRygkRVmPv0JUzZgxlNMKfHy7O1zzhSLBtNwXtzGRNyFO+k1yIk FoWly5/o0mYvW+yU1i5lgBi9Zh5aB5Guq7qsqMoGgDC18u7v+GGAcFhNtwKAXUPy UDf3Ut2RSTitQnyNyl5m =XcED -----END PGP SIGNATURE----- Merge tag 'samsung-soc64-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/arm64 Samsung Exynos ARM64 improvements for v4.6: 1. Remove separate ARCH_EXYNOS7 symbol and consolidate it into one ARCH_EXYNOS. This depends on clk tree: removal of last presence of ARCH_EXYNOS7. * tag 'samsung-soc64-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: EXYNOS: Consolidate ARCH_EXYNOS7 symbol into ARCH_EXYNOS clk: samsung: Don't build ARMv8 clock drivers on ARMv7 clk: samsung: Enable COMPILE_TEST for Samsung clocks clk: Move vendor's Kconfig into CCF menu section clk: mediatek: Fix memory leak on clock init fail clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h clk: xgene: Remove return from void function clk: xgene: Add SoC and PMD PLL clocks with v2 hardware Documentation: Update APM X-Gene clock binding for v2 hardware clk: s2mps11: remove redundant code clk: s2mps11: remove redundant static variables declaration clk: s2mps11: allocate only one structure for clock init clk: s2mps11: merge two for loops in one clk-divider: make sure read-only dividers do not write to their register clk: tango4: rename ARCH_TANGOX to ARCH_TANGO clk: scpi: Fix checking return value of platform_device_register_simple() clk: mvebu: Mark ioremapped memory as __iomem Signed-off-by: Olof Johansson <olof@lixom.net>
172 lines
3.9 KiB
Plaintext
172 lines
3.9 KiB
Plaintext
menu "Platform selection"
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config ARCH_SUNXI
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bool "Allwinner sunxi 64-bit SoC Family"
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help
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This enables support for Allwinner sunxi based SoCs like the A64.
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config ARCH_ALPINE
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bool "Annapurna Labs Alpine platform"
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select ALPINE_MSI
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help
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This enables support for the Annapurna Labs Alpine
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Soc family.
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config ARCH_BCM_IPROC
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bool "Broadcom iProc SoC Family"
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select COMMON_CLK_IPROC
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select PINCTRL
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select ARCH_REQUIRE_GPIOLIB
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help
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This enables support for Broadcom iProc based SoCs
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config ARCH_BERLIN
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bool "Marvell Berlin SoC Family"
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select ARCH_REQUIRE_GPIOLIB
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select DW_APB_ICTL
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select PINCTRL
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help
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This enables support for Marvell Berlin SoC Family
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config ARCH_EXYNOS
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bool "ARMv8 based Samsung Exynos SoC family"
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select COMMON_CLK_SAMSUNG
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select HAVE_S3C2410_WATCHDOG if WATCHDOG
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select HAVE_S3C_RTC if RTC_CLASS
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select PINCTRL
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select PINCTRL_EXYNOS
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help
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This enables support for ARMv8 based Samsung Exynos SoC family.
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config ARCH_LAYERSCAPE
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bool "ARMv8 based Freescale Layerscape SoC family"
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help
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This enables support for the Freescale Layerscape SoC family.
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config ARCH_HISI
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bool "Hisilicon SoC Family"
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help
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This enables support for Hisilicon ARMv8 SoC family
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config ARCH_MEDIATEK
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bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
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select ARM_GIC
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select PINCTRL
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select MTK_TIMER
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help
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Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
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config ARCH_MVEBU
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bool "Marvell EBU SoC Family"
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select ARMADA_AP806_CORE_CLK
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select ARMADA_AP806_RING_CLK
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select MVEBU_ODMI
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help
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This enables support for Marvell EBU familly, including:
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- Armada 3700 SoC Family
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- Armada 7K SoC Family
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- Armada 8K SoC Family
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config ARCH_QCOM
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bool "Qualcomm Platforms"
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select PINCTRL
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help
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This enables support for the ARMv8 based Qualcomm chipsets.
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config ARCH_ROCKCHIP
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bool "Rockchip Platforms"
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select ARCH_HAS_RESET_CONTROLLER
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select ARCH_REQUIRE_GPIOLIB
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select PINCTRL
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select PINCTRL_ROCKCHIP
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select ROCKCHIP_TIMER
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help
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This enables support for the ARMv8 based Rockchip chipsets,
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like the RK3368.
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config ARCH_SEATTLE
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bool "AMD Seattle SoC Family"
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help
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This enables support for AMD Seattle SOC Family
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config ARCH_SHMOBILE
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bool
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config ARCH_RENESAS
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bool "Renesas SoC Platforms"
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select ARCH_SHMOBILE
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select PINCTRL
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select PM
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select PM_GENERIC_DOMAINS
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select RENESAS_IRQC
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help
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This enables support for the ARMv8 based Renesas SoCs.
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config ARCH_R8A7795
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bool "Renesas R-Car H3 SoC Platform"
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depends on ARCH_RENESAS
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help
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This enables support for the Renesas R-Car H3 SoC.
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config ARCH_STRATIX10
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bool "Altera's Stratix 10 SoCFPGA Family"
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help
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This enables support for Altera's Stratix 10 SoCFPGA Family.
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config ARCH_TEGRA
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bool "NVIDIA Tegra SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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select ARCH_REQUIRE_GPIOLIB
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select CLKDEV_LOOKUP
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select CLKSRC_MMIO
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select CLKSRC_OF
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select GENERIC_CLOCKEVENTS
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select HAVE_CLK
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select PINCTRL
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select RESET_CONTROLLER
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help
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This enables support for the NVIDIA Tegra SoC family.
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config ARCH_SPRD
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bool "Spreadtrum SoC platform"
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help
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Support for Spreadtrum ARM based SoCs
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config ARCH_THUNDER
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bool "Cavium Inc. Thunder SoC Family"
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help
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This enables support for Cavium's Thunder Family of SoCs.
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config ARCH_UNIPHIER
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bool "Socionext UniPhier SoC Family"
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select PINCTRL
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help
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This enables support for Socionext UniPhier SoC family.
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config ARCH_VEXPRESS
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bool "ARMv8 software model (Versatile Express)"
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select ARCH_REQUIRE_GPIOLIB
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select COMMON_CLK_VERSATILE
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select POWER_RESET_VEXPRESS
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select VEXPRESS_CONFIG
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help
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This enables support for the ARMv8 software model (Versatile
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Express).
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config ARCH_VULCAN
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bool "Broadcom Vulcan SOC Family"
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help
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This enables support for Broadcom Vulcan SoC Family
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config ARCH_XGENE
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bool "AppliedMicro X-Gene SOC Family"
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help
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This enables support for AppliedMicro X-Gene SOC Family
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config ARCH_ZYNQMP
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bool "Xilinx ZynqMP Family"
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help
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This enables support for Xilinx ZynqMP Family
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endmenu
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