forked from Minki/linux
c7b15c2825
GPIO4_8 is connected to the Ethernet PHY reset line, so populate the 'phy-reset-gpios' property accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
89 lines
1.9 KiB
Plaintext
89 lines
1.9 KiB
Plaintext
/*
|
|
* Copyright 2013 Freescale Semiconductor, Inc.
|
|
*
|
|
* The code contained herein is licensed under the GNU General Public
|
|
* License. You may obtain a copy of the GNU General Public License
|
|
* Version 2 or later at the following locations:
|
|
*
|
|
* http://www.opensource.org/licenses/gpl-license.html
|
|
* http://www.gnu.org/copyleft/gpl.html
|
|
*/
|
|
|
|
/dts-v1/;
|
|
#include "imx25.dtsi"
|
|
|
|
/ {
|
|
model = "Freescale i.MX25 Product Development Kit";
|
|
compatible = "fsl,imx25-pdk", "fsl,imx25";
|
|
|
|
memory {
|
|
reg = <0x80000000 0x4000000>;
|
|
};
|
|
|
|
regulators {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg_fec_3v3: regulator@0 {
|
|
compatible = "regulator-fixed";
|
|
reg = <0>;
|
|
regulator-name = "fec-3v3";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
gpio = <&gpio2 3 0>;
|
|
enable-active-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
&fec {
|
|
phy-mode = "rmii";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_fec>;
|
|
phy-supply = <®_fec_3v3>;
|
|
phy-reset-gpios = <&gpio4 8 0>;
|
|
status = "okay";
|
|
};
|
|
|
|
&iomuxc {
|
|
imx25-pdk {
|
|
pinctrl_fec: fecgrp {
|
|
fsl,pins = <
|
|
MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
|
|
MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0
|
|
MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
|
|
MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
|
|
MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
|
|
MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
|
|
MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
|
|
MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
|
|
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0
|
|
MX25_PAD_A17__GPIO_2_3 0x80000000
|
|
MX25_PAD_D12__GPIO_4_8 0x80000000
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX25_PAD_UART1_RTS__UART1_RTS 0xe0
|
|
MX25_PAD_UART1_CTS__UART1_CTS 0xe0
|
|
MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
|
|
MX25_PAD_UART1_RXD__UART1_RXD 0xc0
|
|
>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&nfc {
|
|
nand-on-flash-bbt;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
|
fsl,uart-has-rtscts;
|
|
status = "okay";
|
|
};
|