forked from Minki/linux
76c47323c1
Equivalent of drm's commit aa61321d4c ("drm/omap: remove rfbi").
The RFBI driver has been marked as BROKEN and has not been
included in the kernel build for many years. Just remove it
(it can be trivially brought back from git repository if
ever needed).
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
875 lines
24 KiB
C
875 lines
24 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2016 Texas Instruments, Inc.
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*/
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#ifndef __OMAPFB_DSS_H
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#define __OMAPFB_DSS_H
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#include <linux/list.h>
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#include <linux/kobject.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/platform_data/omapdss.h>
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#include <video/videomode.h>
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#define DISPC_IRQ_FRAMEDONE (1 << 0)
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#define DISPC_IRQ_VSYNC (1 << 1)
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#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
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#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
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#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
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#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
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#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
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#define DISPC_IRQ_GFX_END_WIN (1 << 7)
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#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
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#define DISPC_IRQ_OCP_ERR (1 << 9)
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#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
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#define DISPC_IRQ_VID1_END_WIN (1 << 11)
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#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
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#define DISPC_IRQ_VID2_END_WIN (1 << 13)
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#define DISPC_IRQ_SYNC_LOST (1 << 14)
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#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
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#define DISPC_IRQ_WAKEUP (1 << 16)
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#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
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#define DISPC_IRQ_VSYNC2 (1 << 18)
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#define DISPC_IRQ_VID3_END_WIN (1 << 19)
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#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
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#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
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#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
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#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
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#define DISPC_IRQ_FRAMEDONETV (1 << 24)
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#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
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#define DISPC_IRQ_WBUNCOMPLETEERROR (1 << 26)
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#define DISPC_IRQ_SYNC_LOST3 (1 << 27)
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#define DISPC_IRQ_VSYNC3 (1 << 28)
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#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
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#define DISPC_IRQ_FRAMEDONE3 (1 << 30)
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struct omap_dss_device;
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struct omap_overlay_manager;
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struct dss_lcd_mgr_config;
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struct snd_aes_iec958;
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struct snd_cea_861_aud_if;
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struct hdmi_avi_infoframe;
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enum omap_display_type {
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OMAP_DISPLAY_TYPE_NONE = 0,
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OMAP_DISPLAY_TYPE_DPI = 1 << 0,
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OMAP_DISPLAY_TYPE_DBI = 1 << 1,
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OMAP_DISPLAY_TYPE_SDI = 1 << 2,
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OMAP_DISPLAY_TYPE_DSI = 1 << 3,
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OMAP_DISPLAY_TYPE_VENC = 1 << 4,
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OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
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OMAP_DISPLAY_TYPE_DVI = 1 << 6,
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};
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enum omap_plane {
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OMAP_DSS_GFX = 0,
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OMAP_DSS_VIDEO1 = 1,
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OMAP_DSS_VIDEO2 = 2,
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OMAP_DSS_VIDEO3 = 3,
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OMAP_DSS_WB = 4,
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};
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enum omap_channel {
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OMAP_DSS_CHANNEL_LCD = 0,
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OMAP_DSS_CHANNEL_DIGIT = 1,
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OMAP_DSS_CHANNEL_LCD2 = 2,
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OMAP_DSS_CHANNEL_LCD3 = 3,
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OMAP_DSS_CHANNEL_WB = 4,
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};
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enum omap_color_mode {
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OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
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OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
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OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
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OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
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OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
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OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
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OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
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OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
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OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
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OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
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OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
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OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
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OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
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OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
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OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
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OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
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OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
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OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
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OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
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};
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enum omap_dss_load_mode {
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OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
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OMAP_DSS_LOAD_CLUT_ONLY = 1,
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OMAP_DSS_LOAD_FRAME_ONLY = 2,
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OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
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};
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enum omap_dss_trans_key_type {
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OMAP_DSS_COLOR_KEY_GFX_DST = 0,
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OMAP_DSS_COLOR_KEY_VID_SRC = 1,
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};
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enum omap_dss_signal_level {
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OMAPDSS_SIG_ACTIVE_LOW,
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OMAPDSS_SIG_ACTIVE_HIGH,
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};
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enum omap_dss_signal_edge {
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OMAPDSS_DRIVE_SIG_FALLING_EDGE,
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OMAPDSS_DRIVE_SIG_RISING_EDGE,
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};
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enum omap_dss_venc_type {
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OMAP_DSS_VENC_TYPE_COMPOSITE,
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OMAP_DSS_VENC_TYPE_SVIDEO,
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};
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enum omap_dss_dsi_pixel_format {
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OMAP_DSS_DSI_FMT_RGB888,
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OMAP_DSS_DSI_FMT_RGB666,
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OMAP_DSS_DSI_FMT_RGB666_PACKED,
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OMAP_DSS_DSI_FMT_RGB565,
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};
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enum omap_dss_dsi_mode {
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OMAP_DSS_DSI_CMD_MODE = 0,
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OMAP_DSS_DSI_VIDEO_MODE,
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};
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enum omap_display_caps {
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OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
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OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
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};
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enum omap_dss_display_state {
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OMAP_DSS_DISPLAY_DISABLED = 0,
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OMAP_DSS_DISPLAY_ACTIVE,
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};
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enum omap_dss_rotation_type {
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OMAP_DSS_ROT_DMA = 1 << 0,
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OMAP_DSS_ROT_VRFB = 1 << 1,
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OMAP_DSS_ROT_TILER = 1 << 2,
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};
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/* clockwise rotation angle */
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enum omap_dss_rotation_angle {
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OMAP_DSS_ROT_0 = 0,
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OMAP_DSS_ROT_90 = 1,
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OMAP_DSS_ROT_180 = 2,
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OMAP_DSS_ROT_270 = 3,
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};
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enum omap_overlay_caps {
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OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
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OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
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OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
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OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
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OMAP_DSS_OVL_CAP_POS = 1 << 4,
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OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
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};
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enum omap_dss_output_id {
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OMAP_DSS_OUTPUT_DPI = 1 << 0,
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OMAP_DSS_OUTPUT_DBI = 1 << 1,
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OMAP_DSS_OUTPUT_SDI = 1 << 2,
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OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
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OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
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OMAP_DSS_OUTPUT_VENC = 1 << 5,
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OMAP_DSS_OUTPUT_HDMI = 1 << 6,
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};
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/* DSI */
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enum omap_dss_dsi_trans_mode {
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/* Sync Pulses: both sync start and end packets sent */
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OMAP_DSS_DSI_PULSE_MODE,
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/* Sync Events: only sync start packets sent */
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OMAP_DSS_DSI_EVENT_MODE,
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/* Burst: only sync start packets sent, pixels are time compressed */
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OMAP_DSS_DSI_BURST_MODE,
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};
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struct omap_dss_dsi_videomode_timings {
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unsigned long hsclk;
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unsigned ndl;
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unsigned bitspp;
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/* pixels */
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u16 hact;
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/* lines */
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u16 vact;
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/* DSI video mode blanking data */
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/* Unit: byte clock cycles */
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u16 hss;
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u16 hsa;
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u16 hse;
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u16 hfp;
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u16 hbp;
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/* Unit: line clocks */
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u16 vsa;
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u16 vfp;
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u16 vbp;
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/* DSI blanking modes */
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int blanking_mode;
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int hsa_blanking_mode;
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int hbp_blanking_mode;
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int hfp_blanking_mode;
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enum omap_dss_dsi_trans_mode trans_mode;
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bool ddr_clk_always_on;
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int window_sync;
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};
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struct omap_dss_dsi_config {
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enum omap_dss_dsi_mode mode;
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enum omap_dss_dsi_pixel_format pixel_format;
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const struct omap_video_timings *timings;
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unsigned long hs_clk_min, hs_clk_max;
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unsigned long lp_clk_min, lp_clk_max;
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bool ddr_clk_always_on;
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enum omap_dss_dsi_trans_mode trans_mode;
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};
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struct omap_video_timings {
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/* Unit: pixels */
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u16 x_res;
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/* Unit: pixels */
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u16 y_res;
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/* Unit: Hz */
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u32 pixelclock;
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/* Unit: pixel clocks */
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u16 hsw; /* Horizontal synchronization pulse width */
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/* Unit: pixel clocks */
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u16 hfp; /* Horizontal front porch */
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/* Unit: pixel clocks */
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u16 hbp; /* Horizontal back porch */
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/* Unit: line clocks */
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u16 vsw; /* Vertical synchronization pulse width */
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/* Unit: line clocks */
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u16 vfp; /* Vertical front porch */
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/* Unit: line clocks */
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u16 vbp; /* Vertical back porch */
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/* Vsync logic level */
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enum omap_dss_signal_level vsync_level;
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/* Hsync logic level */
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enum omap_dss_signal_level hsync_level;
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/* Interlaced or Progressive timings */
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bool interlace;
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/* Pixel clock edge to drive LCD data */
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enum omap_dss_signal_edge data_pclk_edge;
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/* Data enable logic level */
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enum omap_dss_signal_level de_level;
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/* Pixel clock edges to drive HSYNC and VSYNC signals */
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enum omap_dss_signal_edge sync_pclk_edge;
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bool double_pixel;
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};
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/* Hardcoded timings for tv modes. Venc only uses these to
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* identify the mode, and does not actually use the configs
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* itself. However, the configs should be something that
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* a normal monitor can also show */
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extern const struct omap_video_timings omap_dss_pal_timings;
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extern const struct omap_video_timings omap_dss_ntsc_timings;
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struct omap_dss_cpr_coefs {
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s16 rr, rg, rb;
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s16 gr, gg, gb;
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s16 br, bg, bb;
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};
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struct omap_overlay_info {
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dma_addr_t paddr;
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dma_addr_t p_uv_addr; /* for NV12 format */
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u16 screen_width;
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u16 width;
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u16 height;
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enum omap_color_mode color_mode;
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u8 rotation;
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enum omap_dss_rotation_type rotation_type;
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bool mirror;
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u16 pos_x;
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u16 pos_y;
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u16 out_width; /* if 0, out_width == width */
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u16 out_height; /* if 0, out_height == height */
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u8 global_alpha;
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u8 pre_mult_alpha;
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u8 zorder;
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};
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struct omap_overlay {
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struct kobject kobj;
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struct list_head list;
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/* static fields */
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const char *name;
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enum omap_plane id;
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enum omap_color_mode supported_modes;
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enum omap_overlay_caps caps;
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/* dynamic fields */
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struct omap_overlay_manager *manager;
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/*
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* The following functions do not block:
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*
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* is_enabled
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* set_overlay_info
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* get_overlay_info
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*
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* The rest of the functions may block and cannot be called from
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* interrupt context
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*/
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int (*enable)(struct omap_overlay *ovl);
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int (*disable)(struct omap_overlay *ovl);
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bool (*is_enabled)(struct omap_overlay *ovl);
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int (*set_manager)(struct omap_overlay *ovl,
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struct omap_overlay_manager *mgr);
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int (*unset_manager)(struct omap_overlay *ovl);
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int (*set_overlay_info)(struct omap_overlay *ovl,
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struct omap_overlay_info *info);
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void (*get_overlay_info)(struct omap_overlay *ovl,
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struct omap_overlay_info *info);
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int (*wait_for_go)(struct omap_overlay *ovl);
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struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
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};
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struct omap_overlay_manager_info {
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u32 default_color;
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enum omap_dss_trans_key_type trans_key_type;
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u32 trans_key;
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bool trans_enabled;
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bool partial_alpha_enabled;
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bool cpr_enable;
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struct omap_dss_cpr_coefs cpr_coefs;
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};
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struct omap_overlay_manager {
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struct kobject kobj;
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/* static fields */
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const char *name;
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enum omap_channel id;
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struct list_head overlays;
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enum omap_display_type supported_displays;
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enum omap_dss_output_id supported_outputs;
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/* dynamic fields */
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struct omap_dss_device *output;
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/*
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* The following functions do not block:
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*
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* set_manager_info
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* get_manager_info
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* apply
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*
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* The rest of the functions may block and cannot be called from
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* interrupt context
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*/
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int (*set_output)(struct omap_overlay_manager *mgr,
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struct omap_dss_device *output);
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int (*unset_output)(struct omap_overlay_manager *mgr);
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int (*set_manager_info)(struct omap_overlay_manager *mgr,
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struct omap_overlay_manager_info *info);
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void (*get_manager_info)(struct omap_overlay_manager *mgr,
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struct omap_overlay_manager_info *info);
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int (*apply)(struct omap_overlay_manager *mgr);
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int (*wait_for_go)(struct omap_overlay_manager *mgr);
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int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
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struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
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};
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/* 22 pins means 1 clk lane and 10 data lanes */
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#define OMAP_DSS_MAX_DSI_PINS 22
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struct omap_dsi_pin_config {
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int num_pins;
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/*
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* pin numbers in the following order:
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* clk+, clk-
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* data1+, data1-
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* data2+, data2-
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* ...
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*/
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int pins[OMAP_DSS_MAX_DSI_PINS];
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};
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struct omap_dss_writeback_info {
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u32 paddr;
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u32 p_uv_addr;
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u16 buf_width;
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u16 width;
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u16 height;
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enum omap_color_mode color_mode;
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u8 rotation;
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enum omap_dss_rotation_type rotation_type;
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bool mirror;
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u8 pre_mult_alpha;
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};
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struct omapdss_dpi_ops {
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int (*connect)(struct omap_dss_device *dssdev,
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struct omap_dss_device *dst);
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void (*disconnect)(struct omap_dss_device *dssdev,
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struct omap_dss_device *dst);
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int (*enable)(struct omap_dss_device *dssdev);
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void (*disable)(struct omap_dss_device *dssdev);
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int (*check_timings)(struct omap_dss_device *dssdev,
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struct omap_video_timings *timings);
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void (*set_timings)(struct omap_dss_device *dssdev,
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struct omap_video_timings *timings);
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void (*get_timings)(struct omap_dss_device *dssdev,
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struct omap_video_timings *timings);
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void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines);
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};
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struct omapdss_sdi_ops {
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int (*connect)(struct omap_dss_device *dssdev,
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struct omap_dss_device *dst);
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void (*disconnect)(struct omap_dss_device *dssdev,
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struct omap_dss_device *dst);
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int (*enable)(struct omap_dss_device *dssdev);
|
|
void (*disable)(struct omap_dss_device *dssdev);
|
|
|
|
int (*check_timings)(struct omap_dss_device *dssdev,
|
|
struct omap_video_timings *timings);
|
|
void (*set_timings)(struct omap_dss_device *dssdev,
|
|
struct omap_video_timings *timings);
|
|
void (*get_timings)(struct omap_dss_device *dssdev,
|
|
struct omap_video_timings *timings);
|
|
|
|
void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs);
|
|
};
|
|
|
|
struct omapdss_dvi_ops {
|
|
int (*connect)(struct omap_dss_device *dssdev,
|
|
struct omap_dss_device *dst);
|
|
void (*disconnect)(struct omap_dss_device *dssdev,
|
|
struct omap_dss_device *dst);
|
|
|
|
int (*enable)(struct omap_dss_device *dssdev);
|
|
void (*disable)(struct omap_dss_device *dssdev);
|
|
|
|
int (*check_timings)(struct omap_dss_device *dssdev,
|
|
struct omap_video_timings *timings);
|
|
void (*set_timings)(struct omap_dss_device *dssdev,
|
|
struct omap_video_timings *timings);
|
|
void (*get_timings)(struct omap_dss_device *dssdev,
|
|
struct omap_video_timings *timings);
|
|
};
|
|
|
|
struct omapdss_atv_ops {
|
|
int (*connect)(struct omap_dss_device *dssdev,
|
|
struct omap_dss_device *dst);
|
|
void (*disconnect)(struct omap_dss_device *dssdev,
|
|
struct omap_dss_device *dst);
|
|
|
|
int (*enable)(struct omap_dss_device *dssdev);
|
|
void (*disable)(struct omap_dss_device *dssdev);
|
|
|
|
int (*check_timings)(struct omap_dss_device *dssdev,
|
|
struct omap_video_timings *timings);
|
|
void (*set_timings)(struct omap_dss_device *dssdev,
|
|
struct omap_video_timings *timings);
|
|
void (*get_timings)(struct omap_dss_device *dssdev,
|
|
struct omap_video_timings *timings);
|
|
|
|
void (*set_type)(struct omap_dss_device *dssdev,
|
|
enum omap_dss_venc_type type);
|
|
void (*invert_vid_out_polarity)(struct omap_dss_device *dssdev,
|
|
bool invert_polarity);
|
|
|
|
int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
|
|
u32 (*get_wss)(struct omap_dss_device *dssdev);
|
|
};
|
|
|
|
struct omapdss_hdmi_ops {
|
|
int (*connect)(struct omap_dss_device *dssdev,
|
|
struct omap_dss_device *dst);
|
|
void (*disconnect)(struct omap_dss_device *dssdev,
|
|
struct omap_dss_device *dst);
|
|
|
|
int (*enable)(struct omap_dss_device *dssdev);
|
|
void (*disable)(struct omap_dss_device *dssdev);
|
|
|
|
int (*check_timings)(struct omap_dss_device *dssdev,
|
|
struct omap_video_timings *timings);
|
|
void (*set_timings)(struct omap_dss_device *dssdev,
|
|
struct omap_video_timings *timings);
|
|
void (*get_timings)(struct omap_dss_device *dssdev,
|
|
struct omap_video_timings *timings);
|
|
|
|
int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
|
|
bool (*detect)(struct omap_dss_device *dssdev);
|
|
|
|
int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
|
|
int (*set_infoframe)(struct omap_dss_device *dssdev,
|
|
const struct hdmi_avi_infoframe *avi);
|
|
};
|
|
|
|
struct omapdss_dsi_ops {
|
|
int (*connect)(struct omap_dss_device *dssdev,
|
|
struct omap_dss_device *dst);
|
|
void (*disconnect)(struct omap_dss_device *dssdev,
|
|
struct omap_dss_device *dst);
|
|
|
|
int (*enable)(struct omap_dss_device *dssdev);
|
|
void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes,
|
|
bool enter_ulps);
|
|
|
|
/* bus configuration */
|
|
int (*set_config)(struct omap_dss_device *dssdev,
|
|
const struct omap_dss_dsi_config *cfg);
|
|
int (*configure_pins)(struct omap_dss_device *dssdev,
|
|
const struct omap_dsi_pin_config *pin_cfg);
|
|
|
|
void (*enable_hs)(struct omap_dss_device *dssdev, int channel,
|
|
bool enable);
|
|
int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
|
|
|
|
int (*update)(struct omap_dss_device *dssdev, int channel,
|
|
void (*callback)(int, void *), void *data);
|
|
|
|
void (*bus_lock)(struct omap_dss_device *dssdev);
|
|
void (*bus_unlock)(struct omap_dss_device *dssdev);
|
|
|
|
int (*enable_video_output)(struct omap_dss_device *dssdev, int channel);
|
|
void (*disable_video_output)(struct omap_dss_device *dssdev,
|
|
int channel);
|
|
|
|
int (*request_vc)(struct omap_dss_device *dssdev, int *channel);
|
|
int (*set_vc_id)(struct omap_dss_device *dssdev, int channel,
|
|
int vc_id);
|
|
void (*release_vc)(struct omap_dss_device *dssdev, int channel);
|
|
|
|
/* data transfer */
|
|
int (*dcs_write)(struct omap_dss_device *dssdev, int channel,
|
|
u8 *data, int len);
|
|
int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel,
|
|
u8 *data, int len);
|
|
int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
|
|
u8 *data, int len);
|
|
|
|
int (*gen_write)(struct omap_dss_device *dssdev, int channel,
|
|
u8 *data, int len);
|
|
int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel,
|
|
u8 *data, int len);
|
|
int (*gen_read)(struct omap_dss_device *dssdev, int channel,
|
|
u8 *reqdata, int reqlen,
|
|
u8 *data, int len);
|
|
|
|
int (*bta_sync)(struct omap_dss_device *dssdev, int channel);
|
|
|
|
int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev,
|
|
int channel, u16 plen);
|
|
};
|
|
|
|
struct omap_dss_device {
|
|
struct kobject kobj;
|
|
struct device *dev;
|
|
|
|
struct module *owner;
|
|
|
|
struct list_head panel_list;
|
|
|
|
/* alias in the form of "display%d" */
|
|
char alias[16];
|
|
|
|
enum omap_display_type type;
|
|
enum omap_display_type output_type;
|
|
|
|
union {
|
|
struct {
|
|
u8 data_lines;
|
|
} dpi;
|
|
|
|
struct {
|
|
u8 datapairs;
|
|
} sdi;
|
|
|
|
struct {
|
|
int module;
|
|
} dsi;
|
|
|
|
struct {
|
|
enum omap_dss_venc_type type;
|
|
bool invert_polarity;
|
|
} venc;
|
|
} phy;
|
|
|
|
struct {
|
|
struct omap_video_timings timings;
|
|
|
|
enum omap_dss_dsi_pixel_format dsi_pix_fmt;
|
|
enum omap_dss_dsi_mode dsi_mode;
|
|
} panel;
|
|
|
|
struct {
|
|
u8 pixel_size;
|
|
} ctrl;
|
|
|
|
const char *name;
|
|
|
|
/* used to match device to driver */
|
|
const char *driver_name;
|
|
|
|
void *data;
|
|
|
|
struct omap_dss_driver *driver;
|
|
|
|
union {
|
|
const struct omapdss_dpi_ops *dpi;
|
|
const struct omapdss_sdi_ops *sdi;
|
|
const struct omapdss_dvi_ops *dvi;
|
|
const struct omapdss_hdmi_ops *hdmi;
|
|
const struct omapdss_atv_ops *atv;
|
|
const struct omapdss_dsi_ops *dsi;
|
|
} ops;
|
|
|
|
/* helper variable for driver suspend/resume */
|
|
bool activate_after_resume;
|
|
|
|
enum omap_display_caps caps;
|
|
|
|
struct omap_dss_device *src;
|
|
|
|
enum omap_dss_display_state state;
|
|
|
|
/* OMAP DSS output specific fields */
|
|
|
|
struct list_head list;
|
|
|
|
/* DISPC channel for this output */
|
|
enum omap_channel dispc_channel;
|
|
bool dispc_channel_connected;
|
|
|
|
/* output instance */
|
|
enum omap_dss_output_id id;
|
|
|
|
/* the port number in the DT node */
|
|
int port_num;
|
|
|
|
/* dynamic fields */
|
|
struct omap_overlay_manager *manager;
|
|
|
|
struct omap_dss_device *dst;
|
|
};
|
|
|
|
struct omap_dss_driver {
|
|
int (*probe)(struct omap_dss_device *);
|
|
void (*remove)(struct omap_dss_device *);
|
|
|
|
int (*connect)(struct omap_dss_device *dssdev);
|
|
void (*disconnect)(struct omap_dss_device *dssdev);
|
|
|
|
int (*enable)(struct omap_dss_device *display);
|
|
void (*disable)(struct omap_dss_device *display);
|
|
int (*run_test)(struct omap_dss_device *display, int test);
|
|
|
|
int (*update)(struct omap_dss_device *dssdev,
|
|
u16 x, u16 y, u16 w, u16 h);
|
|
int (*sync)(struct omap_dss_device *dssdev);
|
|
|
|
int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
|
|
int (*get_te)(struct omap_dss_device *dssdev);
|
|
|
|
u8 (*get_rotate)(struct omap_dss_device *dssdev);
|
|
int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
|
|
|
|
bool (*get_mirror)(struct omap_dss_device *dssdev);
|
|
int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
|
|
|
|
int (*memory_read)(struct omap_dss_device *dssdev,
|
|
void *buf, size_t size,
|
|
u16 x, u16 y, u16 w, u16 h);
|
|
|
|
void (*get_resolution)(struct omap_dss_device *dssdev,
|
|
u16 *xres, u16 *yres);
|
|
void (*get_dimensions)(struct omap_dss_device *dssdev,
|
|
u32 *width, u32 *height);
|
|
int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
|
|
|
|
int (*check_timings)(struct omap_dss_device *dssdev,
|
|
struct omap_video_timings *timings);
|
|
void (*set_timings)(struct omap_dss_device *dssdev,
|
|
struct omap_video_timings *timings);
|
|
void (*get_timings)(struct omap_dss_device *dssdev,
|
|
struct omap_video_timings *timings);
|
|
|
|
int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
|
|
u32 (*get_wss)(struct omap_dss_device *dssdev);
|
|
|
|
int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
|
|
bool (*detect)(struct omap_dss_device *dssdev);
|
|
|
|
int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
|
|
int (*set_hdmi_infoframe)(struct omap_dss_device *dssdev,
|
|
const struct hdmi_avi_infoframe *avi);
|
|
};
|
|
|
|
#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
|
|
|
|
typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
|
|
|
|
#if IS_ENABLED(CONFIG_FB_OMAP2)
|
|
|
|
enum omapdss_version omapdss_get_version(void);
|
|
bool omapdss_is_initialized(void);
|
|
|
|
int omap_dss_register_driver(struct omap_dss_driver *);
|
|
void omap_dss_unregister_driver(struct omap_dss_driver *);
|
|
|
|
int omapdss_register_display(struct omap_dss_device *dssdev);
|
|
void omapdss_unregister_display(struct omap_dss_device *dssdev);
|
|
|
|
struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev);
|
|
void omap_dss_put_device(struct omap_dss_device *dssdev);
|
|
struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
|
|
struct omap_dss_device *omap_dss_find_device(void *data,
|
|
int (*match)(struct omap_dss_device *dssdev, void *data));
|
|
const char *omapdss_get_default_display_name(void);
|
|
|
|
void videomode_to_omap_video_timings(const struct videomode *vm,
|
|
struct omap_video_timings *ovt);
|
|
void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
|
|
struct videomode *vm);
|
|
|
|
int dss_feat_get_num_mgrs(void);
|
|
int dss_feat_get_num_ovls(void);
|
|
enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
|
|
|
|
|
|
|
|
int omap_dss_get_num_overlay_managers(void);
|
|
struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
|
|
|
|
int omap_dss_get_num_overlays(void);
|
|
struct omap_overlay *omap_dss_get_overlay(int num);
|
|
|
|
int omapdss_register_output(struct omap_dss_device *output);
|
|
void omapdss_unregister_output(struct omap_dss_device *output);
|
|
struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id);
|
|
struct omap_dss_device *omap_dss_find_output(const char *name);
|
|
struct omap_dss_device *omap_dss_find_output_by_port_node(struct device_node *port);
|
|
int omapdss_output_set_device(struct omap_dss_device *out,
|
|
struct omap_dss_device *dssdev);
|
|
int omapdss_output_unset_device(struct omap_dss_device *out);
|
|
|
|
struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev);
|
|
struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev);
|
|
|
|
void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
|
|
u16 *xres, u16 *yres);
|
|
int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
|
|
void omapdss_default_get_timings(struct omap_dss_device *dssdev,
|
|
struct omap_video_timings *timings);
|
|
|
|
int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
|
|
int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
|
|
|
|
int omapdss_compat_init(void);
|
|
void omapdss_compat_uninit(void);
|
|
|
|
static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev)
|
|
{
|
|
return dssdev->src;
|
|
}
|
|
|
|
static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
|
|
{
|
|
return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
|
|
}
|
|
|
|
struct device_node *
|
|
omapdss_of_get_next_port(const struct device_node *parent,
|
|
struct device_node *prev);
|
|
|
|
struct device_node *
|
|
omapdss_of_get_next_endpoint(const struct device_node *parent,
|
|
struct device_node *prev);
|
|
|
|
struct device_node *
|
|
omapdss_of_get_first_endpoint(const struct device_node *parent);
|
|
|
|
struct omap_dss_device *
|
|
omapdss_of_find_source_for_first_ep(struct device_node *node);
|
|
#else
|
|
|
|
static inline enum omapdss_version omapdss_get_version(void)
|
|
{ return OMAPDSS_VER_UNKNOWN; };
|
|
|
|
static inline bool omapdss_is_initialized(void)
|
|
{ return false; };
|
|
|
|
static inline int omap_dispc_register_isr(omap_dispc_isr_t isr,
|
|
void *arg, u32 mask)
|
|
{ return 0; };
|
|
|
|
static inline int omap_dispc_unregister_isr(omap_dispc_isr_t isr,
|
|
void *arg, u32 mask)
|
|
{ return 0; };
|
|
|
|
static inline struct omap_dss_device
|
|
*omap_dss_get_device(struct omap_dss_device *dssdev)
|
|
{ return NULL; };
|
|
|
|
static inline struct omap_dss_device
|
|
*omap_dss_get_next_device(struct omap_dss_device *from)
|
|
{return NULL; };
|
|
|
|
static inline void omap_dss_put_device(struct omap_dss_device *dssdev) {};
|
|
|
|
static inline int omapdss_compat_init(void)
|
|
{ return 0; };
|
|
|
|
static inline void omapdss_compat_uninit(void) {};
|
|
|
|
static inline int omap_dss_get_num_overlay_managers(void)
|
|
{ return 0; };
|
|
|
|
static inline struct omap_overlay_manager *omap_dss_get_overlay_manager(int num)
|
|
{ return NULL; };
|
|
|
|
static inline int omap_dss_get_num_overlays(void)
|
|
{ return 0; };
|
|
|
|
static inline struct omap_overlay *omap_dss_get_overlay(int num)
|
|
{ return NULL; };
|
|
|
|
|
|
#endif /* FB_OMAP2 */
|
|
|
|
|
|
#endif /* __OMAPFB_DSS_H */
|