d2912cb15b
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
487 lines
12 KiB
C
487 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* linux/drivers/media/platform/exynos3250-jpeg/jpeg-hw.h
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Jacek Anaszewski <j.anaszewski@samsung.com>
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*/
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#include <linux/io.h>
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#include <linux/videodev2.h>
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#include <linux/delay.h>
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#include "jpeg-core.h"
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#include "jpeg-regs.h"
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#include "jpeg-hw-exynos3250.h"
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void exynos3250_jpeg_reset(void __iomem *regs)
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{
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u32 reg = 1;
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int count = 1000;
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writel(1, regs + EXYNOS3250_SW_RESET);
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/* no other way but polling for when JPEG IP becomes operational */
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while (reg != 0 && --count > 0) {
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udelay(1);
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cpu_relax();
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reg = readl(regs + EXYNOS3250_SW_RESET);
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}
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reg = 0;
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count = 1000;
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while (reg != 1 && --count > 0) {
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writel(1, regs + EXYNOS3250_JPGDRI);
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udelay(1);
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cpu_relax();
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reg = readl(regs + EXYNOS3250_JPGDRI);
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}
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writel(0, regs + EXYNOS3250_JPGDRI);
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}
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void exynos3250_jpeg_poweron(void __iomem *regs)
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{
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writel(EXYNOS3250_POWER_ON, regs + EXYNOS3250_JPGCLKCON);
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}
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void exynos3250_jpeg_set_dma_num(void __iomem *regs)
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{
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writel(((EXYNOS3250_DMA_MO_COUNT << EXYNOS3250_WDMA_ISSUE_NUM_SHIFT) &
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EXYNOS3250_WDMA_ISSUE_NUM_MASK) |
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((EXYNOS3250_DMA_MO_COUNT << EXYNOS3250_RDMA_ISSUE_NUM_SHIFT) &
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EXYNOS3250_RDMA_ISSUE_NUM_MASK) |
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((EXYNOS3250_DMA_MO_COUNT << EXYNOS3250_ISSUE_GATHER_NUM_SHIFT) &
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EXYNOS3250_ISSUE_GATHER_NUM_MASK),
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regs + EXYNOS3250_DMA_ISSUE_NUM);
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}
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void exynos3250_jpeg_clk_set(void __iomem *base)
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{
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u32 reg;
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reg = readl(base + EXYNOS3250_JPGCMOD) & ~EXYNOS3250_HALF_EN_MASK;
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writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD);
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}
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void exynos3250_jpeg_input_raw_fmt(void __iomem *regs, unsigned int fmt)
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{
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u32 reg;
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reg = readl(regs + EXYNOS3250_JPGCMOD) &
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EXYNOS3250_MODE_Y16_MASK;
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switch (fmt) {
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case V4L2_PIX_FMT_RGB32:
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reg |= EXYNOS3250_MODE_SEL_ARGB8888;
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break;
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case V4L2_PIX_FMT_BGR32:
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reg |= EXYNOS3250_MODE_SEL_ARGB8888 | EXYNOS3250_SRC_SWAP_RGB;
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break;
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case V4L2_PIX_FMT_RGB565:
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reg |= EXYNOS3250_MODE_SEL_RGB565;
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break;
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case V4L2_PIX_FMT_RGB565X:
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reg |= EXYNOS3250_MODE_SEL_RGB565 | EXYNOS3250_SRC_SWAP_RGB;
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break;
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case V4L2_PIX_FMT_YUYV:
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reg |= EXYNOS3250_MODE_SEL_422_1P_LUM_CHR;
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break;
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case V4L2_PIX_FMT_YVYU:
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reg |= EXYNOS3250_MODE_SEL_422_1P_LUM_CHR |
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EXYNOS3250_SRC_SWAP_UV;
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break;
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case V4L2_PIX_FMT_UYVY:
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reg |= EXYNOS3250_MODE_SEL_422_1P_CHR_LUM;
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break;
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case V4L2_PIX_FMT_VYUY:
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reg |= EXYNOS3250_MODE_SEL_422_1P_CHR_LUM |
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EXYNOS3250_SRC_SWAP_UV;
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break;
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case V4L2_PIX_FMT_NV12:
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reg |= EXYNOS3250_MODE_SEL_420_2P | EXYNOS3250_SRC_NV12;
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break;
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case V4L2_PIX_FMT_NV21:
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reg |= EXYNOS3250_MODE_SEL_420_2P | EXYNOS3250_SRC_NV21;
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break;
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case V4L2_PIX_FMT_YUV420:
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reg |= EXYNOS3250_MODE_SEL_420_3P;
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break;
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default:
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break;
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}
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writel(reg, regs + EXYNOS3250_JPGCMOD);
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}
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void exynos3250_jpeg_set_y16(void __iomem *regs, bool y16)
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{
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u32 reg;
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reg = readl(regs + EXYNOS3250_JPGCMOD);
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if (y16)
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reg |= EXYNOS3250_MODE_Y16;
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else
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reg &= ~EXYNOS3250_MODE_Y16_MASK;
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writel(reg, regs + EXYNOS3250_JPGCMOD);
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}
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void exynos3250_jpeg_proc_mode(void __iomem *regs, unsigned int mode)
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{
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u32 reg, m;
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if (mode == S5P_JPEG_ENCODE)
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m = EXYNOS3250_PROC_MODE_COMPR;
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else
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m = EXYNOS3250_PROC_MODE_DECOMPR;
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reg = readl(regs + EXYNOS3250_JPGMOD);
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reg &= ~EXYNOS3250_PROC_MODE_MASK;
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reg |= m;
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writel(reg, regs + EXYNOS3250_JPGMOD);
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}
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void exynos3250_jpeg_subsampling_mode(void __iomem *regs, unsigned int mode)
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{
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u32 reg, m = 0;
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switch (mode) {
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case V4L2_JPEG_CHROMA_SUBSAMPLING_444:
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m = EXYNOS3250_SUBSAMPLING_MODE_444;
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break;
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case V4L2_JPEG_CHROMA_SUBSAMPLING_422:
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m = EXYNOS3250_SUBSAMPLING_MODE_422;
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break;
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case V4L2_JPEG_CHROMA_SUBSAMPLING_420:
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m = EXYNOS3250_SUBSAMPLING_MODE_420;
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break;
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}
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reg = readl(regs + EXYNOS3250_JPGMOD);
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reg &= ~EXYNOS3250_SUBSAMPLING_MODE_MASK;
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reg |= m;
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writel(reg, regs + EXYNOS3250_JPGMOD);
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}
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unsigned int exynos3250_jpeg_get_subsampling_mode(void __iomem *regs)
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{
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return readl(regs + EXYNOS3250_JPGMOD) &
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EXYNOS3250_SUBSAMPLING_MODE_MASK;
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}
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void exynos3250_jpeg_dri(void __iomem *regs, unsigned int dri)
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{
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u32 reg;
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reg = dri & EXYNOS3250_JPGDRI_MASK;
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writel(reg, regs + EXYNOS3250_JPGDRI);
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}
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void exynos3250_jpeg_qtbl(void __iomem *regs, unsigned int t, unsigned int n)
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{
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unsigned long reg;
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reg = readl(regs + EXYNOS3250_QHTBL);
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reg &= ~EXYNOS3250_QT_NUM_MASK(t);
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reg |= (n << EXYNOS3250_QT_NUM_SHIFT(t)) &
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EXYNOS3250_QT_NUM_MASK(t);
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writel(reg, regs + EXYNOS3250_QHTBL);
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}
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void exynos3250_jpeg_htbl_ac(void __iomem *regs, unsigned int t)
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{
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unsigned long reg;
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reg = readl(regs + EXYNOS3250_QHTBL);
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reg &= ~EXYNOS3250_HT_NUM_AC_MASK(t);
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/* this driver uses table 0 for all color components */
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reg |= (0 << EXYNOS3250_HT_NUM_AC_SHIFT(t)) &
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EXYNOS3250_HT_NUM_AC_MASK(t);
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writel(reg, regs + EXYNOS3250_QHTBL);
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}
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void exynos3250_jpeg_htbl_dc(void __iomem *regs, unsigned int t)
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{
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unsigned long reg;
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reg = readl(regs + EXYNOS3250_QHTBL);
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reg &= ~EXYNOS3250_HT_NUM_DC_MASK(t);
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/* this driver uses table 0 for all color components */
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reg |= (0 << EXYNOS3250_HT_NUM_DC_SHIFT(t)) &
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EXYNOS3250_HT_NUM_DC_MASK(t);
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writel(reg, regs + EXYNOS3250_QHTBL);
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}
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void exynos3250_jpeg_set_y(void __iomem *regs, unsigned int y)
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{
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u32 reg;
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reg = y & EXYNOS3250_JPGY_MASK;
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writel(reg, regs + EXYNOS3250_JPGY);
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}
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void exynos3250_jpeg_set_x(void __iomem *regs, unsigned int x)
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{
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u32 reg;
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reg = x & EXYNOS3250_JPGX_MASK;
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writel(reg, regs + EXYNOS3250_JPGX);
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}
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#if 0 /* Currently unused */
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unsigned int exynos3250_jpeg_get_y(void __iomem *regs)
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{
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return readl(regs + EXYNOS3250_JPGY);
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}
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unsigned int exynos3250_jpeg_get_x(void __iomem *regs)
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{
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return readl(regs + EXYNOS3250_JPGX);
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}
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#endif
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void exynos3250_jpeg_interrupts_enable(void __iomem *regs)
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{
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u32 reg;
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reg = readl(regs + EXYNOS3250_JPGINTSE);
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reg |= (EXYNOS3250_JPEG_DONE_EN |
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EXYNOS3250_WDMA_DONE_EN |
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EXYNOS3250_RDMA_DONE_EN |
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EXYNOS3250_ENC_STREAM_INT_EN |
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EXYNOS3250_CORE_DONE_EN |
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EXYNOS3250_ERR_INT_EN |
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EXYNOS3250_HEAD_INT_EN);
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writel(reg, regs + EXYNOS3250_JPGINTSE);
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}
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void exynos3250_jpeg_enc_stream_bound(void __iomem *regs, unsigned int size)
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{
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u32 reg;
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reg = size & EXYNOS3250_ENC_STREAM_BOUND_MASK;
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writel(reg, regs + EXYNOS3250_ENC_STREAM_BOUND);
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}
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void exynos3250_jpeg_output_raw_fmt(void __iomem *regs, unsigned int fmt)
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{
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u32 reg;
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switch (fmt) {
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case V4L2_PIX_FMT_RGB32:
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reg = EXYNOS3250_OUT_FMT_ARGB8888;
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break;
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case V4L2_PIX_FMT_BGR32:
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reg = EXYNOS3250_OUT_FMT_ARGB8888 | EXYNOS3250_OUT_SWAP_RGB;
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break;
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case V4L2_PIX_FMT_RGB565:
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reg = EXYNOS3250_OUT_FMT_RGB565;
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break;
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case V4L2_PIX_FMT_RGB565X:
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reg = EXYNOS3250_OUT_FMT_RGB565 | EXYNOS3250_OUT_SWAP_RGB;
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break;
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case V4L2_PIX_FMT_YUYV:
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reg = EXYNOS3250_OUT_FMT_422_1P_LUM_CHR;
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break;
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case V4L2_PIX_FMT_YVYU:
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reg = EXYNOS3250_OUT_FMT_422_1P_LUM_CHR |
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EXYNOS3250_OUT_SWAP_UV;
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break;
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case V4L2_PIX_FMT_UYVY:
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reg = EXYNOS3250_OUT_FMT_422_1P_CHR_LUM;
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break;
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case V4L2_PIX_FMT_VYUY:
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reg = EXYNOS3250_OUT_FMT_422_1P_CHR_LUM |
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EXYNOS3250_OUT_SWAP_UV;
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break;
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case V4L2_PIX_FMT_NV12:
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reg = EXYNOS3250_OUT_FMT_420_2P | EXYNOS3250_OUT_NV12;
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break;
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case V4L2_PIX_FMT_NV21:
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reg = EXYNOS3250_OUT_FMT_420_2P | EXYNOS3250_OUT_NV21;
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break;
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case V4L2_PIX_FMT_YUV420:
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reg = EXYNOS3250_OUT_FMT_420_3P;
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break;
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default:
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reg = 0;
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break;
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}
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writel(reg, regs + EXYNOS3250_OUTFORM);
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}
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void exynos3250_jpeg_jpgadr(void __iomem *regs, unsigned int addr)
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{
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writel(addr, regs + EXYNOS3250_JPG_JPGADR);
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}
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void exynos3250_jpeg_imgadr(void __iomem *regs, struct s5p_jpeg_addr *img_addr)
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{
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writel(img_addr->y, regs + EXYNOS3250_LUMA_BASE);
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writel(img_addr->cb, regs + EXYNOS3250_CHROMA_BASE);
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writel(img_addr->cr, regs + EXYNOS3250_CHROMA_CR_BASE);
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}
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void exynos3250_jpeg_stride(void __iomem *regs, unsigned int img_fmt,
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unsigned int width)
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{
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u32 reg_luma = 0, reg_cr = 0, reg_cb = 0;
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switch (img_fmt) {
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case V4L2_PIX_FMT_RGB32:
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reg_luma = 4 * width;
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break;
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case V4L2_PIX_FMT_RGB565:
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case V4L2_PIX_FMT_RGB565X:
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case V4L2_PIX_FMT_YUYV:
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case V4L2_PIX_FMT_YVYU:
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case V4L2_PIX_FMT_UYVY:
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case V4L2_PIX_FMT_VYUY:
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reg_luma = 2 * width;
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break;
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case V4L2_PIX_FMT_NV12:
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case V4L2_PIX_FMT_NV21:
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reg_luma = width;
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reg_cb = reg_luma;
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break;
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case V4L2_PIX_FMT_YUV420:
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reg_luma = width;
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reg_cb = reg_cr = reg_luma / 2;
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break;
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default:
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break;
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}
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writel(reg_luma, regs + EXYNOS3250_LUMA_STRIDE);
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writel(reg_cb, regs + EXYNOS3250_CHROMA_STRIDE);
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writel(reg_cr, regs + EXYNOS3250_CHROMA_CR_STRIDE);
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}
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void exynos3250_jpeg_offset(void __iomem *regs, unsigned int x_offset,
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unsigned int y_offset)
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{
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u32 reg;
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reg = (y_offset << EXYNOS3250_LUMA_YY_OFFSET_SHIFT) &
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EXYNOS3250_LUMA_YY_OFFSET_MASK;
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reg |= (x_offset << EXYNOS3250_LUMA_YX_OFFSET_SHIFT) &
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EXYNOS3250_LUMA_YX_OFFSET_MASK;
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writel(reg, regs + EXYNOS3250_LUMA_XY_OFFSET);
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reg = (y_offset << EXYNOS3250_CHROMA_YY_OFFSET_SHIFT) &
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EXYNOS3250_CHROMA_YY_OFFSET_MASK;
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reg |= (x_offset << EXYNOS3250_CHROMA_YX_OFFSET_SHIFT) &
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EXYNOS3250_CHROMA_YX_OFFSET_MASK;
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writel(reg, regs + EXYNOS3250_CHROMA_XY_OFFSET);
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reg = (y_offset << EXYNOS3250_CHROMA_CR_YY_OFFSET_SHIFT) &
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EXYNOS3250_CHROMA_CR_YY_OFFSET_MASK;
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reg |= (x_offset << EXYNOS3250_CHROMA_CR_YX_OFFSET_SHIFT) &
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EXYNOS3250_CHROMA_CR_YX_OFFSET_MASK;
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writel(reg, regs + EXYNOS3250_CHROMA_CR_XY_OFFSET);
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}
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void exynos3250_jpeg_coef(void __iomem *base, unsigned int mode)
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{
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if (mode == S5P_JPEG_ENCODE) {
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writel(EXYNOS3250_JPEG_ENC_COEF1,
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base + EXYNOS3250_JPG_COEF(1));
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writel(EXYNOS3250_JPEG_ENC_COEF2,
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base + EXYNOS3250_JPG_COEF(2));
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writel(EXYNOS3250_JPEG_ENC_COEF3,
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base + EXYNOS3250_JPG_COEF(3));
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} else {
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writel(EXYNOS3250_JPEG_DEC_COEF1,
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base + EXYNOS3250_JPG_COEF(1));
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writel(EXYNOS3250_JPEG_DEC_COEF2,
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base + EXYNOS3250_JPG_COEF(2));
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writel(EXYNOS3250_JPEG_DEC_COEF3,
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base + EXYNOS3250_JPG_COEF(3));
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}
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}
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void exynos3250_jpeg_start(void __iomem *regs)
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{
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writel(1, regs + EXYNOS3250_JSTART);
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}
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void exynos3250_jpeg_rstart(void __iomem *regs)
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{
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writel(1, regs + EXYNOS3250_JRSTART);
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}
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unsigned int exynos3250_jpeg_get_int_status(void __iomem *regs)
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{
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return readl(regs + EXYNOS3250_JPGINTST);
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}
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void exynos3250_jpeg_clear_int_status(void __iomem *regs,
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unsigned int value)
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{
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writel(value, regs + EXYNOS3250_JPGINTST);
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}
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unsigned int exynos3250_jpeg_operating(void __iomem *regs)
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{
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return readl(regs + S5P_JPGOPR) & EXYNOS3250_JPGOPR_MASK;
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}
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unsigned int exynos3250_jpeg_compressed_size(void __iomem *regs)
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{
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return readl(regs + EXYNOS3250_JPGCNT) & EXYNOS3250_JPGCNT_MASK;
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}
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void exynos3250_jpeg_dec_stream_size(void __iomem *regs,
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unsigned int size)
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{
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writel(size & EXYNOS3250_DEC_STREAM_MASK,
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regs + EXYNOS3250_DEC_STREAM_SIZE);
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}
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void exynos3250_jpeg_dec_scaling_ratio(void __iomem *regs,
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unsigned int sratio)
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{
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switch (sratio) {
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case 1:
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default:
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sratio = EXYNOS3250_DEC_SCALE_FACTOR_8_8;
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break;
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case 2:
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sratio = EXYNOS3250_DEC_SCALE_FACTOR_4_8;
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break;
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case 4:
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sratio = EXYNOS3250_DEC_SCALE_FACTOR_2_8;
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break;
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case 8:
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sratio = EXYNOS3250_DEC_SCALE_FACTOR_1_8;
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break;
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}
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|
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writel(sratio & EXYNOS3250_DEC_SCALE_FACTOR_MASK,
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regs + EXYNOS3250_DEC_SCALING_RATIO);
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}
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void exynos3250_jpeg_set_timer(void __iomem *regs, unsigned int time_value)
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{
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time_value &= EXYNOS3250_TIMER_INIT_MASK;
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writel(EXYNOS3250_TIMER_INT_STAT | time_value,
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regs + EXYNOS3250_TIMER_SE);
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}
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unsigned int exynos3250_jpeg_get_timer_status(void __iomem *regs)
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{
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return readl(regs + EXYNOS3250_TIMER_ST);
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}
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void exynos3250_jpeg_clear_timer_status(void __iomem *regs)
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|
{
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writel(EXYNOS3250_TIMER_INT_STAT, regs + EXYNOS3250_TIMER_ST);
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}
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