c49836f05a
Allwinner NAND controllers can make use of DMA to enhance the I/O throughput thanks to ECC pipelining. DMA handling with A23/A33 NAND IP is a bit different than with the older SoCs, hence the introduction of a new compatible to handle: * the differences between register offsets, * the burst length change from 4 to minimum 8, * drive SRAM accesses through the AHB bus instead of the MBUS. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> |
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| .. | ||
| onenand | ||
| raw | ||
| spi | ||
| bbt.c | ||
| core.c | ||
| Kconfig | ||
| Makefile | ||