b5b8a7cf14
This patch updates the PMCs for AMD Zen1 core based processors (Family
17h; Models 0 through 2F) to be in accordance with PMCs as
documented in the latest versions of the AMD Processor Programming
Reference [1], [2] and [3]. Note that some events, such as FPU pipe
assignment are missing in [1], and therefore [3] is included for full
coverage of events.
PMCs added:
fpu_pipe_assignment.dual{0|1|2|3}
fpu_pipe_assignment.total{0|1|2|3}
ls_mab_alloc.dc_prefetcher
ls_mab_alloc.stores
ls_mab_alloc.loads
bp_dyn_ind_pred
bp_de_redirect
PMC removed:
ex_ret_cond_misp
Cumulative counts, fpu_pipe_assignment.total and
fpu_pipe_assignment.dual, existed in v1, but did expose port-level
counters.
ex_ret_cond_misp has been removed as it has been removed from the latest
versions of the PPR, and when tested, always seems to sample zero as
tested on a Ryzen 3400G system.
[1]: Processor Programming Reference (PPR) for AMD Family 17h Models
01h,08h, Revision B2 Processors, 54945 Rev 3.03 - Jun 14, 2019.
[2]: Processor Programming Reference (PPR) for AMD Family 17h Model 18h,
Revision B1 Processors, 55570-B1 Rev 3.14 - Sep 26, 2019.
[3]: OSRR for AMD Family 17h processors, Models 00h-2Fh, 56255 Rev 3.03 - July, 2018
All of the PPRs can be found at:
https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Vijay Thakkar <vijaythakkar@me.com>
Acked-by: Kim Phillips <kim.phillips@amd.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Jon Grimm <jon.grimm@amd.com>
Cc: Martin Liška <mliska@suse.cz>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: vijay thakkar <vijaythakkar@me.com>
Link: http://lore.kernel.org/lkml/20200318190002.307290-4-vijaythakkar@me.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
57 lines
2.2 KiB
JSON
57 lines
2.2 KiB
JSON
[
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{
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"EventName": "ic_oc_mode_switch.oc_ic_mode_switch",
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"EventCode": "0x28a",
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"BriefDescription": "OC Mode Switch. OC to IC mode switch.",
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"UMask": "0x2"
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},
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{
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"EventName": "ic_oc_mode_switch.ic_oc_mode_switch",
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"EventCode": "0x28a",
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"BriefDescription": "OC Mode Switch. IC to OC mode switch.",
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"UMask": "0x1"
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},
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{
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"EventName": "de_dis_dispatch_token_stalls0.retire_token_stall",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailable.",
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"UMask": "0x40"
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},
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{
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"EventName": "de_dis_dispatch_token_stalls0.agsq_token_stall",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable.",
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"UMask": "0x20"
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},
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{
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"EventName": "de_dis_dispatch_token_stalls0.alu_token_stall",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailable.",
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"UMask": "0x10"
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},
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{
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"EventName": "de_dis_dispatch_token_stalls0.alsq3_0_token_stall",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3_0 Tokens unavailable.",
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"UMask": "0x8"
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},
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{
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"EventName": "de_dis_dispatch_token_stalls0.alsq3_token_stall",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3 Tokens unavailable.",
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"UMask": "0x4"
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},
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{
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"EventName": "de_dis_dispatch_token_stalls0.alsq2_token_stall",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 2 Tokens unavailable.",
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"UMask": "0x2"
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},
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{
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"EventName": "de_dis_dispatch_token_stalls0.alsq1_token_stall",
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"EventCode": "0xaf",
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"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 1 Tokens unavailable.",
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"UMask": "0x1"
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}
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]
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