Manivannan Sadhasivam c457ac029e PCI: qcom-ep: Gate Master AXI clock to MHI bus during L1SS ...

During L1SS, gate the Master clock supplied to the MHI bus to save power.

Link: https://lore.kernel.org/r/20220914075350.7992-7-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>

2022-10-05 16:17:45 +02:00

22 KiB

Raw Blame History

View Raw