Eric Yang c43f89f81c drm/amd/display: put back front end initialization sequence ... [Why] Seamless boot optimization removed proper front end power off sequence. In driver disable enable case, this causes driver to power gate hubp and dpp while there is still memory fetching going on, this can cause invalid memory requests to be generated which will hang data fabric. [How] Put back proper front end power off sequence Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-07-18 14:27:25 -05:00
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amdgpu_dm	drm/amd/display: add functionality to get pipe CRC source.	2019-07-18 14:18:09 -05:00
dc	drm/amd/display: put back front end initialization sequence	2019-07-18 14:27:25 -05:00
include	drm/amd/display:Use Pixel clock in 100Hz units for HDMI Audio wall clock DTO	2019-07-18 14:18:09 -05:00
modules	Merge branch 'drm-next' into drm-next-5.3	2019-06-25 08:42:25 -05:00
Kconfig	drm/amd/display: Add drm_audio_component support to amdgpu_dm	2019-07-11 14:37:24 -05:00
Makefile	drm/amd/display: move clk_mgr files to right place	2019-05-31 10:39:31 -05:00
TODO	drm/amd/display: Convert remaining loggers off dc_logger	2018-07-13 14:48:42 -05:00