linux/arch/mips/include/asm/netlogic/xlp-hal
Jayachandran C c24a8a7a99 MIPS: Netlogic: Add MSI support for XLP
Add MSI chip and MSIX chip definitions.

For MSI, we map the link interrupt to a MSI link IRQ which will
do a second level of dispatch based on the MSI status register.

The MSI chip definitions use the MSI enable register to enable
and disable the MSI irqs.

For MSI-X, we split the 32 available MSI-X vectors across the
four PCIe links (8 each). These PIC interrupts generate an IRQ
per link which uses a second level dispatch as well.

The MSI-X chip definition uses the standard functions to enable
and disable interrupts.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6270/
2014-01-24 22:39:46 +01:00
..
bridge.h MIPS: Netlogic: Read memory from DRAM BARs 2013-09-03 23:22:18 +02:00
cpucontrol.h MIPS: Netlogic: Split XLP L1 i-cache among threads 2013-02-17 00:15:20 +01:00
iomap.h MIPS: Netlogic: Add support for USB on XLP2xx 2013-09-03 23:22:20 +02:00
pcibus.h MIPS: Netlogic: Add MSI support for XLP 2014-01-24 22:39:46 +01:00
pic.h MIPS: Netlogic: Add MSI support for XLP 2014-01-24 22:39:46 +01:00
sys.h MIPS: Netlogic: XLP2XX CPU and PIC frequency 2013-09-03 23:22:19 +02:00
uart.h MIPS: Whitespace cleanup. 2013-02-01 10:00:22 +01:00
xlp.h MIPS: Netlogic: Add MSI support for XLP 2014-01-24 22:39:46 +01:00