991dcb89ca
Based on a bspec update the DMC firmware's flip queue handling events need to be disabled before enabling DC5/6. i915 doesn't use the flip queue feature atm, so disable it already after loading the firmware. This removes some overhead of the event handler which runs at a 1 kHz frequency. Bspec: 49193, 72486, 72487 v2: - Fix the DMC pipe A register offsets for GEN12. - Disable the events on DG2 only on pipe A..D . v3: (Lucas) - Add TODO: to clarify the disabling sequence on all D13+ - s/intel_dmc_has_fw_payload/has_dmc_id_fw/ - s/simple_flipq/flipq/ - s/_GEN12,_GEN13/TGL_,ADLP_/ - s/MAINDMC/DMC/ v4: - Only disable flip queues on TGL/DG2, as on other platforms the corresponding event handlers don't exist. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> # v1 Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220521130808.637449-1-imre.deak@intel.com
88 lines
2.8 KiB
C
88 lines
2.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __INTEL_DMC_REGS_H__
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#define __INTEL_DMC_REGS_H__
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#include "i915_reg_defs.h"
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#define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
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#define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
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#define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000
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#define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000
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#define __PIPEDMC_REG_MMIO_BASE(i915, dmc_id) \
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((DISPLAY_VER(i915) >= 13 ? _ADLP_PIPEDMC_REG_MMIO_BASE_A : \
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_TGL_PIPEDMC_REG_MMIO_BASE_A) + \
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0x400 * ((dmc_id) - 1))
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#define __DMC_REG_MMIO_BASE 0x8f000
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#define _DMC_REG_MMIO_BASE(i915, dmc_id) \
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((dmc_id) == DMC_FW_MAIN ? __DMC_REG_MMIO_BASE : \
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__PIPEDMC_REG_MMIO_BASE(i915, dmc_id))
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#define _DMC_REG(i915, dmc_id, reg) \
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((reg) - __DMC_REG_MMIO_BASE + _DMC_REG_MMIO_BASE(i915, dmc_id))
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#define _DMC_EVT_HTP_0 0x8f004
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#define DMC_EVT_HTP(i915, dmc_id, handler) \
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_MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_HTP_0) + 4 * (handler))
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#define _DMC_EVT_CTL_0 0x8f034
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#define DMC_EVT_CTL(i915, dmc_id, handler) \
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_MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_CTL_0) + 4 * (handler))
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#define DMC_EVT_CTL_ENABLE REG_BIT(31)
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#define DMC_EVT_CTL_RECURRING REG_BIT(30)
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#define DMC_EVT_CTL_TYPE_MASK REG_GENMASK(17, 16)
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#define DMC_EVT_CTL_TYPE_LEVEL_0 0
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#define DMC_EVT_CTL_TYPE_LEVEL_1 1
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#define DMC_EVT_CTL_TYPE_EDGE_1_0 2
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#define DMC_EVT_CTL_TYPE_EDGE_0_1 3
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#define DMC_EVT_CTL_EVENT_ID_MASK REG_GENMASK(15, 8)
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#define DMC_EVT_CTL_EVENT_ID_FALSE 0x01
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/* An event handler scheduled to run at a 1 kHz frequency. */
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#define DMC_EVT_CTL_EVENT_ID_CLK_MSEC 0xbf
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#define DMC_HTP_ADDR_SKL 0x00500034
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#define DMC_SSP_BASE _MMIO(0x8F074)
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#define DMC_HTP_SKL _MMIO(0x8F004)
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#define DMC_LAST_WRITE _MMIO(0x8F034)
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#define DMC_LAST_WRITE_VALUE 0xc003b400
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#define DMC_MMIO_START_RANGE 0x80000
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#define DMC_MMIO_END_RANGE 0x8FFFF
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#define DMC_V1_MMIO_START_RANGE 0x80000
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#define TGL_MAIN_MMIO_START 0x8F000
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#define TGL_MAIN_MMIO_END 0x8FFFF
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#define _TGL_PIPEA_MMIO_START 0x92000
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#define _TGL_PIPEA_MMIO_END 0x93FFF
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#define _TGL_PIPEB_MMIO_START 0x96000
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#define _TGL_PIPEB_MMIO_END 0x97FFF
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#define ADLP_PIPE_MMIO_START 0x5F000
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#define ADLP_PIPE_MMIO_END 0x5FFFF
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#define TGL_PIPE_MMIO_START(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_START,\
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_TGL_PIPEB_MMIO_START)
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#define TGL_PIPE_MMIO_END(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_END,\
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_TGL_PIPEB_MMIO_END)
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#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
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#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
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#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)
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#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
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#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
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#define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
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#define TGL_DMC_DEBUG3 _MMIO(0x101090)
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#define DG1_DMC_DEBUG3 _MMIO(0x13415c)
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#endif /* __INTEL_DMC_REGS_H__ */
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